| Age | Commit message (Collapse) | Author |
|---|
|
We currently have the same code in hush.c and main.c. This brings the
code into one place.
As an added feature, if the command function returns CMD_RET_USAGE then
cmd_process() will print a usage message for the command before
returning the standard failure code of 1.
ARM code size increases about 32 bytes with this clean-up.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
There is a nasty interleave of #ifdefs in hush.c where the two code
paths have different indents. Remove this ickiness.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
We should aim for a single point of entry to the commands, whichever
parser is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
This saves about 1KB of code space on ARM with CONFIG_SYS_HUSH_PARSER
defined.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Boards can select either the 'built-in' parser or the hush parser. We
should not call builtin_run_command() if we are using the hush parser.
We use run_command() instead, since it knows how to call the correct
parser.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
This is a more sensible name, so rename it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
The current run_command() is only one of the parsing options - the other
is hush. We should not call run_command() when the hush parser is being
used. So we rename this function to better explain its purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
It really isn't clear why this is here and there is no comment, so
drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
Building the eNET_SRAM board fails for me:
sc520_timer.c: In function 'sc520_udelay':
sc520_timer.c:81:7: error: variable 'temp' set but not used
[-Werror=unused-but-set-variable]
cc1: all warnings being treated as errors
make[1]: *** [sc520_timer.o] Error 1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
|
|
Signed-off-by: Thomas Weber <weber@corscience.de>
|
|
The reference implementation of the PCI initialization code almost
everywhere contain this fragile loop of "a few usecs", and its
use of volatile variables to delay a number of bus cycles is indeed
uncertain.
Reading the manual "Integrator/AP Users Guide", page 5-15 it is
clearly stated:
"Wait until 230ms after the end of the reset period before
accessing V360EPC internal registers. The V360EPC supports the
use of a serial configuration PROM and the software must wait for
the device to detect the absence of this PROM before accessing any
registers. The required delay is a function of the PCI Clock, but
at the lower frequency (25MHz) is 230ms".
So let's simply wait 230ms per the spec.
This solves the compilation error that looked like this:
pci.c: In function ‘pci_init_board’:
pci.c:286:18: warning: variable ‘j’ set but not used
Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in <pci.h>
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.
Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
This seems to be unsigned char for no good reason. Tidy this up and
remove the casts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
There doesn't seem to be any reason for using uchar here, so change it
to char. This fixes a warning:
pointer targets in passing argument 1 of 'sprintf' differ in signedness
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
Following the corresponding Linux code, this patch relaxes reset timings
waiting at least 100ms after power to the ports. There are some reports
that it helps make enumeration work better on some high speed devices.
Furthermore, the wait is only done once after power has been enabled
on all ports.
CC: Remy Bohmer <linux@bohmer.net>
CC: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
|
|
This moves keyboard polling logic from USB HCD drivers into USB
keyboard driver. Remove usb_event_poll() as keyboard polling was
the only user of this API. With this patch USB keyboard works with
EHCI controllers again. Tested on a tegra2 seaboard.
Signed-off-by: Allen Martin <amartin@nvidia.com>
|
|
If CONSOLE_MUX is enabled, reevaluate console stdin when USB keyboard
device is detected.
Signed-off-by: Allen Martin <amartin@nvidia.com>
|
|
When keys are pressed on the numeric keypad, emit key codes for the numbers,
operators, dot and enter.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
|
|
When doing a "GET_REPORT" request on the keyboard control endpoint,
the report ID should 0 (ie report ID not used) rather than 1
as reports are not used in boot mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
|
|
Fix the crash when running several times usb_init() with a USB ethernet
device plugged.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Wolfgang Grandegger <wg@denx.de>
|
|
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Acked-by: Mike Frysinger <vapier@gentoo.org>
|
|
* 'master' of git://git.denx.de/u-boot-nand-flash:
cmd_nand.c: Fix 'nand dump' after latest MTD resync
mtd/nand:Fix wrong usage of is_blank() in fsl_ifc_run_command
mtd/nand: Fix IFC driver to support 2K NAND page
nand: reinstate lazy bad block scanning
Revert "nand: make 1-bit software ECC configurable"
|
|
* 'master' of git://git.denx.de/u-boot-nds32:
nds32/board.c: add PCI prompt at boot up
nds32/ag101/watchdog.S: add linkage support
nds32: add linkage support
|
|
Fix build error for ethernut5 board due to prototype change
for function board_mmc_getcd().
ethernut5.c:238: error: conflicting types for 'board_mmc_getcd'
u-boot/include/mmc.h:318: note: previous declaration of 'board_mmc_getcd'
was here
make[2]: *** [ethernut5.o] Error 1
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Tim Schendekehl <tim.schendekehl@egnite.de>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: egnite GmbH <info@egnite.de>
|
|
With 2a8e0fc nand_do_read_ops changed in behavior slightly (keeping in sync
with the kernel which did this change in b64d39d8) such that the OOB data is
always copied into oobbuf and never appended to datbuf. Within U-Boot only
the nand_dump function (for the dump nand subcommand) was expecting the OOB
data to only be appended to datbuf. So we now change nand_dump to not
malloc extra space, correct the comment about datbuf and OOB data and switch
the pointer to oobbuf before printing.
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
|
Freescale IFC NAND Machine calculates ECC on 512byte sector and same is used in
fsl_ifc_run_command() during ECC status verification. Also this sector is passed
to is_blank() for blank checking. It is wrong at first place because
is_blank()'s implementation checks for Page size and OOB area size.
is_blank() should be called per page for main and OOB area verification.
Variables name are redefined to avoid confusion between buffer and ecc sector.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
|
1) OOB area should be updated irrespective of NAND page size. Earlier it was
updated only for 512byte NAND page.
2) During OOB update fbcr should be equal to OOB size.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
|
commit 2a8e0fc8b3dc31a3c571e439fbf04b882c8986be ("nand: Merge changes
from Linux nand driver") accidentally reverted commit
13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde ("NAND: Scan bad blocks
lazily.").
Reinstate the change, as amended by commit
ff49ea8977b56916edd5b1766d9939010e30b181 ("NAND: Mark the BBT as scanned
prior to calling scan_bbt.").
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
|
This reverts commit 4fee6c2f295f932b8febdc7ce8731ba045695fa5.
It breaks boards that currently rely on soft-ecc, as pointed out here:
http://patchwork.ozlabs.org/patch/140872/
The reverted patch should be resubmitted with documentation, and with the
CONFIG_MTD_ECC_SOFT selected from every board that needs it. We could
start by looking at what NAND driver the board selects, and whether
that driver ever asks for soft ECC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
|
add PCI prompt at boot up for probing PCI device
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
|
|
Add linkage support to watchdog.S.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
|
|
Add linkage support.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
|
|
Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.
Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f4080952798413fb63bb4134b22c57623a
However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.
As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.
Signed-off-by: Aneesh V <aneesh@ti.com>
|
|
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
|
|
Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
|
|
Add PREBOOT, SILENT_CONSOLE and DEVICE_NULLDEV for release
build. Fixed bug in CONFIG_SYS_HUSH_PARSER define.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
|
|
The video setup for the Epson display is provided. Addtionally
some extra info is displayed next to the Linux logo.
Make get_cpu_rev() publicly available (added to sys_proto.h).
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
|
|
size of environment must match erasable block size in the flash.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
|
|
Define CONFIG_PHY_MICREL, and
minimize the tx clock delay.
There is an issue with 1000 baseTx mode on early revs
of the SabreLite boards. The center tap pin 9 of the mag RJ45
USB combo was connected to the 3.3 filtered supply. Letting
this pin float solved the problem. Symptoms of the problem
were packets with many extra zeroes tacked on the end, and random
bit flips causing a high rate of CRC errors. 10/100 baseTx worked
fine on all revs. To disable 1000 baseTx for these boards, simply
define the environment variable disable_giga. ie.
setenv disable_giga 1
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
|
|
Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
|
|
Add the gigabit phy KSZ9021.
Also, add function ksz9021_phy_extended_write
/_read for access to the phys extended registers.
The environment variable "disable_giga"
can be used to disable 1000baseTx.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
|
|
Surround non PHYLIB routines miiphy_restart_aneg
and miiphy_wait_aneg with ifndef CONFIG_PHYLIB.
When later PHYLIB is required it is easy to delete
the non-PHYLIB code. This separation idea
came from Andy Fleming.
fec_miiphy_read, and fec_miiphy_write changed to
fec_phy_read, and fec_phy_write with argument changes.
Deprecated miiphy_register is no longer used. Both
old and new PHYLIB code now use mdio_register.
Cleanup some debug prints.
Inline function fec_miiphy_fec_to_eth is no longer necessary.
Moved to the single call location.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
|
|
Define FEC_QUIRK_ENET_MAC and add to
arch-mx6/imx-regs.h
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
|
|
The Integrator/CP config file was very outdated and gives a
non functional U-Boot. So:
- Set the CONFIG_ARCH_CINTEGRATOR arch flag correctly
- Add proper core module configuration options
- Skip cluttered command lista and just include
<config_cmd_default.h>
- Kill off #if 0 network section and insert some example
configuration that simply just boots from the network
using TFTP if available.
- Delete flash control registers that have no business
in this config file. These are already moved down to
board/armltd/integrator/integrator-sc.h
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The PCI support for the Integrator AP has apparently never
been finished and I strongly suspect that it has never worked,
so let's fix it. This is a list of the more or less
un-splittable changes done in this driver rewrite:
- Replace the register definitions stashed into the config
file (!) with a copy if the register file from the Linux
kernels arch/arm/include/asm/hardware/pci_v3.h
- Delete the unreadable gigantic macros that perform the
config accesses and replace them with copyedited code from
Linux arch/arm/mach-integrator/pci_v3.c
- Rewrite the rest of the setup code to use the
v3_[read|write][lwb]() accessors.
- Enable PCI by default in the AP board configuration.
- Fix checkpatch warnings and make code more conformant.
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
The U-Boot startup infrastructure already makes sure pci_init() is
called at a proper time, calling it again from within the board
setup code will not make things better.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
|
Signed-off-by: Detlev Zundel <dzu@denx.de>
CC: Stefano Babic <sbabic@denx.de>
|
|
davinci_dm6467Tevm
In commit 2d575e46859dd9127a9cec731ace77523e6ea2ab a separate header
file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h.
The substantial difference between the davinci_dm6467evm and the
davinci_dm6467Tevm configuration is a single bit in the hardware revision
that is passed to the Linux kernel and davinci_dm6467evm has
REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a
REFCLK_FREQ = 33000000.
This patch removes include/configs/davinci_dm6467Tevm.h. Instead the
include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and
renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined
in boards.cfg.
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Tom Rini <trini@ti.com>
|
