diff options
Diffstat (limited to 'arch/arm/include/asm/arch-vybrid/iomux.h')
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/iomux.h | 322 |
1 files changed, 322 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vybrid/iomux.h b/arch/arm/include/asm/arch-vybrid/iomux.h new file mode 100644 index 0000000000..e5ec5ddc03 --- /dev/null +++ b/arch/arm/include/asm/arch-vybrid/iomux.h @@ -0,0 +1,322 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_VYBRID_IOMUX_H__ +#define __MACH_VYBRID_IOMUX_H__ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/vybrid-regs.h> +#include <asm/arch/vybrid-pins.h> + +#define IOMUXC_PAD_000 (IOMUXC_BASE_ADDR + 0x0000) +#define IOMUXC_PAD_001 (IOMUXC_BASE_ADDR + 0x0004) +#define IOMUXC_PAD_002 (IOMUXC_BASE_ADDR + 0x0008) +#define IOMUXC_PAD_003 (IOMUXC_BASE_ADDR + 0x000C) +#define IOMUXC_PAD_004 (IOMUXC_BASE_ADDR + 0x0010) +#define IOMUXC_PAD_005 (IOMUXC_BASE_ADDR + 0x0014) +#define IOMUXC_PAD_006 (IOMUXC_BASE_ADDR + 0x0018) +#define IOMUXC_PAD_007 (IOMUXC_BASE_ADDR + 0x001C) +#define IOMUXC_PAD_008 (IOMUXC_BASE_ADDR + 0x0020) +#define IOMUXC_PAD_009 (IOMUXC_BASE_ADDR + 0x0024) +#define IOMUXC_PAD_010 (IOMUXC_BASE_ADDR + 0x0028) +#define IOMUXC_PAD_011 (IOMUXC_BASE_ADDR + 0x002C) +#define IOMUXC_PAD_012 (IOMUXC_BASE_ADDR + 0x0030) +#define IOMUXC_PAD_013 (IOMUXC_BASE_ADDR + 0x0034) +#define IOMUXC_PAD_014 (IOMUXC_BASE_ADDR + 0x0038) +#define IOMUXC_PAD_015 (IOMUXC_BASE_ADDR + 0x003C) +#define IOMUXC_PAD_016 (IOMUXC_BASE_ADDR + 0x0040) +#define IOMUXC_PAD_017 (IOMUXC_BASE_ADDR + 0x0044) +#define IOMUXC_PAD_018 (IOMUXC_BASE_ADDR + 0x0048) +#define IOMUXC_PAD_019 (IOMUXC_BASE_ADDR + 0x004C) +#define IOMUXC_PAD_020 (IOMUXC_BASE_ADDR + 0x0050) +#define IOMUXC_PAD_021 (IOMUXC_BASE_ADDR + 0x0054) +#define IOMUXC_PAD_022 (IOMUXC_BASE_ADDR + 0x0058) +#define IOMUXC_PAD_023 (IOMUXC_BASE_ADDR + 0x005C) +#define IOMUXC_PAD_024 (IOMUXC_BASE_ADDR + 0x0060) +#define IOMUXC_PAD_025 (IOMUXC_BASE_ADDR + 0x0064) +#define IOMUXC_PAD_026 (IOMUXC_BASE_ADDR + 0x0068) +#define IOMUXC_PAD_027 (IOMUXC_BASE_ADDR + 0x006C) +#define IOMUXC_PAD_028 (IOMUXC_BASE_ADDR + 0x0070) +#define IOMUXC_PAD_029 (IOMUXC_BASE_ADDR + 0x0074) +#define IOMUXC_PAD_030 (IOMUXC_BASE_ADDR + 0x0078) +#define IOMUXC_PAD_031 (IOMUXC_BASE_ADDR + 0x007C) +#define IOMUXC_PAD_032 (IOMUXC_BASE_ADDR + 0x0080) +#define IOMUXC_PAD_033 (IOMUXC_BASE_ADDR + 0x0084) +#define IOMUXC_PAD_034 (IOMUXC_BASE_ADDR + 0x0088) +#define IOMUXC_PAD_035 (IOMUXC_BASE_ADDR + 0x008C) +#define IOMUXC_PAD_036 (IOMUXC_BASE_ADDR + 0x0090) +#define IOMUXC_PAD_037 (IOMUXC_BASE_ADDR + 0x0094) +#define IOMUXC_PAD_038 (IOMUXC_BASE_ADDR + 0x0098) +#define IOMUXC_PAD_039 (IOMUXC_BASE_ADDR + 0x009C) +#define IOMUXC_PAD_040 (IOMUXC_BASE_ADDR + 0x00A0) +#define IOMUXC_PAD_041 (IOMUXC_BASE_ADDR + 0x00A4) +#define IOMUXC_PAD_042 (IOMUXC_BASE_ADDR + 0x00A8) +#define IOMUXC_PAD_043 (IOMUXC_BASE_ADDR + 0x00AC) +#define IOMUXC_PAD_044 (IOMUXC_BASE_ADDR + 0x00B0) +#define IOMUXC_PAD_045 (IOMUXC_BASE_ADDR + 0x00B4) +#define IOMUXC_PAD_046 (IOMUXC_BASE_ADDR + 0x00B8) +#define IOMUXC_PAD_047 (IOMUXC_BASE_ADDR + 0x00BC) +#define IOMUXC_PAD_048 (IOMUXC_BASE_ADDR + 0x00C0) +#define IOMUXC_PAD_049 (IOMUXC_BASE_ADDR + 0x00C4) +#define IOMUXC_PAD_050 (IOMUXC_BASE_ADDR + 0x00C8) +#define IOMUXC_PAD_051 (IOMUXC_BASE_ADDR + 0x00CC) +#define IOMUXC_PAD_052 (IOMUXC_BASE_ADDR + 0x00D0) +#define IOMUXC_PAD_053 (IOMUXC_BASE_ADDR + 0x00D4) +#define IOMUXC_PAD_054 (IOMUXC_BASE_ADDR + 0x00D8) +#define IOMUXC_PAD_055 (IOMUXC_BASE_ADDR + 0x00DC) +#define IOMUXC_PAD_056 (IOMUXC_BASE_ADDR + 0x00E0) +#define IOMUXC_PAD_057 (IOMUXC_BASE_ADDR + 0x00E4) +#define IOMUXC_PAD_058 (IOMUXC_BASE_ADDR + 0x00E8) +#define IOMUXC_PAD_059 (IOMUXC_BASE_ADDR + 0x00EC) +#define IOMUXC_PAD_060 (IOMUXC_BASE_ADDR + 0x00F0) +#define IOMUXC_PAD_061 (IOMUXC_BASE_ADDR + 0x00F4) +#define IOMUXC_PAD_062 (IOMUXC_BASE_ADDR + 0x00F8) +#define IOMUXC_PAD_063 (IOMUXC_BASE_ADDR + 0x00FC) +#define IOMUXC_PAD_064 (IOMUXC_BASE_ADDR + 0x0100) +#define IOMUXC_PAD_065 (IOMUXC_BASE_ADDR + 0x0104) +#define IOMUXC_PAD_066 (IOMUXC_BASE_ADDR + 0x0108) +#define IOMUXC_PAD_067 (IOMUXC_BASE_ADDR + 0x010C) +#define IOMUXC_PAD_068 (IOMUXC_BASE_ADDR + 0x0110) +#define IOMUXC_PAD_069 (IOMUXC_BASE_ADDR + 0x0114) +#define IOMUXC_PAD_070 (IOMUXC_BASE_ADDR + 0x0118) +#define IOMUXC_PAD_071 (IOMUXC_BASE_ADDR + 0x011C) +#define IOMUXC_PAD_072 (IOMUXC_BASE_ADDR + 0x0120) +#define IOMUXC_PAD_073 (IOMUXC_BASE_ADDR + 0x0124) +#define IOMUXC_PAD_074 (IOMUXC_BASE_ADDR + 0x0128) +#define IOMUXC_PAD_075 (IOMUXC_BASE_ADDR + 0x012C) +#define IOMUXC_PAD_076 (IOMUXC_BASE_ADDR + 0x0130) +#define IOMUXC_PAD_077 (IOMUXC_BASE_ADDR + 0x0134) +#define IOMUXC_PAD_078 (IOMUXC_BASE_ADDR + 0x0138) +#define IOMUXC_PAD_079 (IOMUXC_BASE_ADDR + 0x013C) +#define IOMUXC_PAD_080 (IOMUXC_BASE_ADDR + 0x0140) +#define IOMUXC_PAD_081 (IOMUXC_BASE_ADDR + 0x0144) +#define IOMUXC_PAD_082 (IOMUXC_BASE_ADDR + 0x0148) +#define IOMUXC_PAD_083 (IOMUXC_BASE_ADDR + 0x014C) +#define IOMUXC_PAD_084 (IOMUXC_BASE_ADDR + 0x0150) +#define IOMUXC_PAD_085 (IOMUXC_BASE_ADDR + 0x0154) +#define IOMUXC_PAD_086 (IOMUXC_BASE_ADDR + 0x0158) +#define IOMUXC_PAD_087 (IOMUXC_BASE_ADDR + 0x015C) +#define IOMUXC_PAD_088 (IOMUXC_BASE_ADDR + 0x0160) +#define IOMUXC_PAD_089 (IOMUXC_BASE_ADDR + 0x0164) +#define IOMUXC_PAD_090 (IOMUXC_BASE_ADDR + 0x0168) +#define IOMUXC_PAD_091 (IOMUXC_BASE_ADDR + 0x016C) +#define IOMUXC_PAD_092 (IOMUXC_BASE_ADDR + 0x0170) +#define IOMUXC_PAD_093 (IOMUXC_BASE_ADDR + 0x0174) +#define IOMUXC_PAD_094 (IOMUXC_BASE_ADDR + 0x0178) +#define IOMUXC_PAD_095 (IOMUXC_BASE_ADDR + 0x017C) +#define IOMUXC_PAD_096 (IOMUXC_BASE_ADDR + 0x0180) +#define IOMUXC_PAD_097 (IOMUXC_BASE_ADDR + 0x0184) +#define IOMUXC_PAD_098 (IOMUXC_BASE_ADDR + 0x0188) +#define IOMUXC_PAD_099 (IOMUXC_BASE_ADDR + 0x018C) +#define IOMUXC_PAD_100 (IOMUXC_BASE_ADDR + 0x0190) +#define IOMUXC_PAD_101 (IOMUXC_BASE_ADDR + 0x0194) +#define IOMUXC_PAD_102 (IOMUXC_BASE_ADDR + 0x0198) +#define IOMUXC_PAD_103 (IOMUXC_BASE_ADDR + 0x019C) +#define IOMUXC_PAD_104 (IOMUXC_BASE_ADDR + 0x01A0) +#define IOMUXC_PAD_105 (IOMUXC_BASE_ADDR + 0x01A4) +#define IOMUXC_PAD_106 (IOMUXC_BASE_ADDR + 0x01A8) +#define IOMUXC_PAD_107 (IOMUXC_BASE_ADDR + 0x01AC) +#define IOMUXC_PAD_108 (IOMUXC_BASE_ADDR + 0x01B0) +#define IOMUXC_PAD_109 (IOMUXC_BASE_ADDR + 0x01B4) +#define IOMUXC_PAD_110 (IOMUXC_BASE_ADDR + 0x01B8) +#define IOMUXC_PAD_111 (IOMUXC_BASE_ADDR + 0x01BC) +#define IOMUXC_PAD_112 (IOMUXC_BASE_ADDR + 0x01C0) +#define IOMUXC_PAD_113 (IOMUXC_BASE_ADDR + 0x01C4) +#define IOMUXC_PAD_114 (IOMUXC_BASE_ADDR + 0x01C8) +#define IOMUXC_PAD_115 (IOMUXC_BASE_ADDR + 0x01CC) +#define IOMUXC_PAD_116 (IOMUXC_BASE_ADDR + 0x01D0) +#define IOMUXC_PAD_117 (IOMUXC_BASE_ADDR + 0x01D4) +#define IOMUXC_PAD_118 (IOMUXC_BASE_ADDR + 0x01D8) +#define IOMUXC_PAD_119 (IOMUXC_BASE_ADDR + 0x01DC) +#define IOMUXC_PAD_120 (IOMUXC_BASE_ADDR + 0x01E0) +#define IOMUXC_PAD_121 (IOMUXC_BASE_ADDR + 0x01E4) +#define IOMUXC_PAD_122 (IOMUXC_BASE_ADDR + 0x01E8) +#define IOMUXC_PAD_123 (IOMUXC_BASE_ADDR + 0x01EC) +#define IOMUXC_PAD_124 (IOMUXC_BASE_ADDR + 0x01F0) +#define IOMUXC_PAD_125 (IOMUXC_BASE_ADDR + 0x01F4) +#define IOMUXC_PAD_126 (IOMUXC_BASE_ADDR + 0x01F8) +#define IOMUXC_PAD_127 (IOMUXC_BASE_ADDR + 0x01FC) +#define IOMUXC_PAD_128 (IOMUXC_BASE_ADDR + 0x0200) +#define IOMUXC_PAD_129 (IOMUXC_BASE_ADDR + 0x0204) +#define IOMUXC_PAD_130 (IOMUXC_BASE_ADDR + 0x0208) +#define IOMUXC_PAD_131 (IOMUXC_BASE_ADDR + 0x020C) +#define IOMUXC_PAD_132 (IOMUXC_BASE_ADDR + 0x0210) +#define IOMUXC_PAD_133 (IOMUXC_BASE_ADDR + 0x0214) +#define IOMUXC_PAD_134 (IOMUXC_BASE_ADDR + 0x0218) + +#define IOMUXC_DDR_RESET (IOMUXC_BASE_ADDR + 0x021C) +#define IOMUXC_DDR_A15 (IOMUXC_BASE_ADDR + 0x0220) +#define IOMUXC_DDR_A14 (IOMUXC_BASE_ADDR + 0x0224) +#define IOMUXC_DDR_A13 (IOMUXC_BASE_ADDR + 0x0228) +#define IOMUXC_DDR_A12 (IOMUXC_BASE_ADDR + 0x022C) +#define IOMUXC_DDR_A11 (IOMUXC_BASE_ADDR + 0x0230) +#define IOMUXC_DDR_A10 (IOMUXC_BASE_ADDR + 0x0234) +#define IOMUXC_DDR_A9 (IOMUXC_BASE_ADDR + 0x0238) +#define IOMUXC_DDR_A8 (IOMUXC_BASE_ADDR + 0x023C) +#define IOMUXC_DDR_A7 (IOMUXC_BASE_ADDR + 0x0240) +#define IOMUXC_DDR_A6 (IOMUXC_BASE_ADDR + 0x0244) +#define IOMUXC_DDR_A5 (IOMUXC_BASE_ADDR + 0x0248) +#define IOMUXC_DDR_A4 (IOMUXC_BASE_ADDR + 0x024C) +#define IOMUXC_DDR_A3 (IOMUXC_BASE_ADDR + 0x0250) +#define IOMUXC_DDR_A2 (IOMUXC_BASE_ADDR + 0x0254) +#define IOMUXC_DDR_A1 (IOMUXC_BASE_ADDR + 0x0258) +#define IOMUXC_DDR_A0 (IOMUXC_BASE_ADDR + 0x025C) + +#define IOMUXC_DDR_BA2 (IOMUXC_BASE_ADDR + 0x0260) +#define IOMUXC_DDR_BA1 (IOMUXC_BASE_ADDR + 0x0264) +#define IOMUXC_DDR_BA0 (IOMUXC_BASE_ADDR + 0x0268) + +#define IOMUXC_DDR_CAS (IOMUXC_BASE_ADDR + 0x026C) + +#define IOMUXC_DDR_CKE (IOMUXC_BASE_ADDR + 0x0270) + +#define IOMUXC_DDR_CLK (IOMUXC_BASE_ADDR + 0x0274) + +#define IOMUXC_DDR_CS (IOMUXC_BASE_ADDR + 0x0278) + +#define IOMUXC_DDR_D15 (IOMUXC_BASE_ADDR + 0x027C) +#define IOMUXC_DDR_D14 (IOMUXC_BASE_ADDR + 0x0280) +#define IOMUXC_DDR_D13 (IOMUXC_BASE_ADDR + 0x0284) +#define IOMUXC_DDR_D12 (IOMUXC_BASE_ADDR + 0x0288) +#define IOMUXC_DDR_D11 (IOMUXC_BASE_ADDR + 0x028C) +#define IOMUXC_DDR_D10 (IOMUXC_BASE_ADDR + 0x0290) +#define IOMUXC_DDR_D9 (IOMUXC_BASE_ADDR + 0x0294) +#define IOMUXC_DDR_D8 (IOMUXC_BASE_ADDR + 0x0298) +#define IOMUXC_DDR_D7 (IOMUXC_BASE_ADDR + 0x029C) +#define IOMUXC_DDR_D6 (IOMUXC_BASE_ADDR + 0x02A0) +#define IOMUXC_DDR_D5 (IOMUXC_BASE_ADDR + 0x02A4) +#define IOMUXC_DDR_D4 (IOMUXC_BASE_ADDR + 0x02A8) +#define IOMUXC_DDR_D3 (IOMUXC_BASE_ADDR + 0x02AC) +#define IOMUXC_DDR_D2 (IOMUXC_BASE_ADDR + 0x02B0) +#define IOMUXC_DDR_D1 (IOMUXC_BASE_ADDR + 0x02B4) +#define IOMUXC_DDR_D0 (IOMUXC_BASE_ADDR + 0x02B8) + +#define IOMUXC_DDR_DQM1 (IOMUXC_BASE_ADDR + 0x02BC) +#define IOMUXC_DDR_DQM0 (IOMUXC_BASE_ADDR + 0x02C0) + +#define IOMUXC_DDR_DQS1 (IOMUXC_BASE_ADDR + 0x02C4) +#define IOMUXC_DDR_DQS0 (IOMUXC_BASE_ADDR + 0x02C8) + +#define IOMUXC_DDR_RAS (IOMUXC_BASE_ADDR + 0x02CC) +#define IOMUXC_DDR_WE (IOMUXC_BASE_ADDR + 0x02D0) + +#define IOMUXC_DDR_ODT0 (IOMUXC_BASE_ADDR + 0x02D4) +#define IOMUXC_DDR_ODT1 (IOMUXC_BASE_ADDR + 0x02D8) + +#define IOMUXC_DDR_DDRBYTE1 (IOMUXC_BASE_ADDR + 0x02DC) +#define IOMUXC_DDR_DDRBYTE0 (IOMUXC_BASE_ADDR + 0x02E0) + +#define IOMUXC_SDHC_DUMMY1 (IOMUXC_BASE_ADDR + 0x02E4) +#define IOMUXC_SDHC_DUMMY2 (IOMUXC_BASE_ADDR + 0x02E8) + +#define IOMUXC_AUD_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02EC) +#define IOMUXC_ENET_EXTCLK_INP (IOMUXC_BASE_ADDR + 0x02F0) +#define IOMUXC_ENET_TSCLK_INP (IOMUXC_BASE_ADDR + 0x02F4) + +typedef struct pad_iomux { + u8 mod; + u8 spd; + u8 sre; + u8 ode; + u8 hys; + u8 dse; + u8 pus; + u8 pke; + u8 pue; + u8 obe; + u8 ibe; +} pad_iomux_t; + +#define PADIOMUX_SET(val, mod, spd, sre, ode, hys, dse, pus, pke, pue, obe, ibe)\ + (val = (((mod & 7) << 20) | ((spd & 3) << 12) | \ + ((sre & 1) << 11) | ((ode & 1) << 10) | \ + ((hys & 1) << 9) | ((dse & 7) << 6) | \ + ((pus & 3) << 4) | ((pke & 1) << 3) | \ + ((pue & 1) << 2) | ((obe & 1) << 1) | \ + (ibe & 1))) + +#define DDRIOMUX_SET(inp, trim, hys, dse, pus, pke, pue) \ + (((inp & 1) << 16) | ((trim & 3) << 14) | \ + ((hys & 1) << 9) | ((dse & 7) << 6) | \ + ((pus & 3) << 4) | ((pke & 1) << 3) | \ + ((pue & 1) << 2)) + +#define MUX_MODE_ALT0 0x00 +#define MUX_MODE_ALT1 0x01 +#define MUX_MODE_ALT2 0x02 +#define MUX_MODE_ALT3 0x03 +#define MUX_MODE_ALT4 0x04 +#define MUX_MODE_ALT5 0x05 +#define MUX_MODE_ALT6 0x06 +#define MUX_MODE_ALT7 0x07 + +#define MUX_SPD_50MHZ 0x00 +#define MUX_SPD_100MHZ 0x02 +#define MUX_SPD_200MHZ 0x03 + +#define MUX_SRE_SLOW 0 +#define MUX_SRE_FAST 1 + +#define MUX_ODE_CMOS 0 +#define MUX_ODE_OPEN 1 + +#define MUX_HYS_CMOS 0 +#define MUX_HYS_SCHMITT 1 + +#define MUX_DSE_20_OHM 7 +#define MUX_DSE_25_OHM 6 +#define MUX_DSE_30_OHM 5 +#define MUX_DSE_37_OHM 4 +#define MUX_DSE_50_OHM 3 +#define MUX_DSE_75_OHM 2 +#define MUX_DSE_150_OHM 1 +#define MUX_DSE_DIS 0 + +#define MUX_PUS_22KOHM_UP 3 +#define MUX_PUS_100KOHM_UP 2 +#define MUX_PUS_47KOHM_UP 1 +#define MUX_PUS_100KOHM_DN 0 + +#define MUX_PKE_EN 1 +#define MUX_PKE_DIS 0 + +#define MUX_PUE_PULLEN 1 +#define MUX_PUE_KEEPEREN 0 + +#define MUX_OBE_EN 1 +#define MUX_OBE_DIS 0 + +#define MUX_IBE_EN 1 +#define MUX_IBE_DIS 0 + +#define MUX_DDR_INPUT_DIFF 1 +#define MUX_DDR_INPUT_CMOS 0 + +#define MUX_DDR_TRIM_150PS 3 +#define MUX_DDR_TRIM_100PS 2 +#define MUX_DDR_TRIM_50PS 1 +#define MUX_DDR_TRIM_MIN 0 + +void pad_iomux_set(u32 pad_addr, pad_iomux_t *padio); + +#endif /* __MACH_VYBRID_IOMUX_H__ */ |