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-rw-r--r--arch/arm/cpu/armv7/vybrid-common/Makefile47
-rw-r--r--arch/arm/cpu/armv7/vybrid-common/cpu.c137
-rw-r--r--arch/arm/cpu/armv7/vybrid-common/speed.c41
-rw-r--r--arch/arm/cpu/armv7/vybrid-common/timer.c141
4 files changed, 366 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/vybrid-common/Makefile b/arch/arm/cpu/armv7/vybrid-common/Makefile
new file mode 100644
index 0000000000..9ae8997873
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libvybrid-common.o
+
+COBJS = timer.o cpu.o speed.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c b/arch/arm/cpu/armv7/vybrid-common/cpu.c
new file mode 100644
index 0000000000..865c01fc58
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+
+static char *get_reset_cause(void)
+{
+ char resetcause[32][64] = {"POR",
+ "Cortex A5 WDOG Timer Reset",
+ 0,
+ "CA5 WDOG reset",
+ "CM4 WDOG reset",
+ "JTAG HIGH-Z",
+ 0,
+ "External Reset",
+ "1.2V supply below 0.7V",
+ "HP regulator's LVD",
+ "ULP regulator's LVD",
+ "3.3V main supply is unstable",
+ "LP regulator's LVD",
+ 0,
+ 0,
+ 0,
+ "MDM-AP system reset request is set",
+ "Hard Fail State of System Security Monitor",
+ "SRC_SCR SW Reset is set",
+ "Platform's CSU alarm event",
+ 0,
+ 0,
+ 0,
+ 0,
+ "Anadig regulator 1.1V unstable",
+ "Anadig regulator 2.5V unstable",
+ "Anadig regulator 3.0V unstable",
+ "CMU even when FOSC freq less than 40MHz",
+ "CMU event when BUS freq is out of range",
+ "No clock is detected on FOSC",
+ "No clock is detected on SOSC",
+ "CM4 is in lockup"};
+ char buf[512] = {0}, *pbuf;
+ u32 cause;
+ int i, bit;
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+ cause = readl(&src_regs->srsr);
+ writel(cause, &src_regs->srsr);
+
+ pbuf = &buf[0];
+
+ for (i = 0; i < 32; i++) {
+ bit = 1 << i;
+ if ((cause & bit) == bit) {
+ if (resetcause[i][0] != NULL)
+ pbuf += sprintf(pbuf, "%s, ", resetcause[i]);
+ }
+ }
+
+ if (buf[0] == NULL)
+ return 0;
+
+ return &buf[0];
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+ printf("CPU: Freescale VyBrid %x family rev%d.%d at %d MHz\n",
+ (cpurev & 0xFFF000) >> 12,
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0,
+ vybrid_get_clock(VYBRID_ARM_CLK) / 1000000);
+ if (get_reset_cause() != NULL)
+ printf("Reset cause: %s\n", get_reset_cause());
+ return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+ rc = mcffec_initialize(bis);
+
+ return rc;
+}
+
+/* Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FSL_ESDHC
+ return fsl_esdhc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
+void reset_cpu(ulong addr)
+{
+ __raw_writew(4, WDOG_A5_BASE_ADDR);
+}
diff --git a/arch/arm/cpu/armv7/vybrid-common/speed.c b/arch/arm/cpu/armv7/vybrid-common/speed.c
new file mode 100644
index 0000000000..df768b37e4
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/speed.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/vybrid-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_clocks(void)
+{
+ gd->bus_clk = 66000000;
+ gd->ipg_clk = 66000000;
+#ifdef CONFIG_FSL_ESDHC
+ gd->sdhc_clk = 132000000;
+#endif
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/vybrid-common/timer.c b/arch/arm/cpu/armv7/vybrid-common/timer.c
new file mode 100644
index 0000000000..6062a41e71
--- /dev/null
+++ b/arch/arm/cpu/armv7/vybrid-common/timer.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/vybrid-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define timestamp (gd->tbl)
+#define timerticks (gd->tbu)
+#define lastinc (gd->lastinc)
+static unsigned long ltmstamp = 0;
+
+#define CONFIG_TMR_USEPIT
+#ifdef CONFIG_TMR_USEPIT
+
+unsigned long long _usec2ticks(unsigned long long usec);
+
+int timer_init(void)
+{
+ ulong usecs;
+ ulong ticks;
+
+ timestamp = 0;
+
+ /*
+ * nsecs conversion = (1/ipg_clk) * 10^9
+ * equivalent to 1000 / (ipg_clk / 10^6)
+ */
+ usecs = (gd->ipg_clk / 1000000);
+ ticks = 1000 / usecs;
+
+ clrbits_le32(PIT_MCR, 2); /* enable PIT */
+
+ /* ticks per 10 us = 10000 us / usecs = cycles time */
+ timerticks = (10 * 1000) / ticks;
+
+ __raw_writel(0xFFFFFFFF, PIT_LDVAL1);
+ __raw_writel(0, PIT_TCTRL1);
+ __raw_writel(4, PIT_TCTRL1);
+ __raw_writel(5, PIT_TCTRL1);
+ __raw_writel(timerticks, PIT_LDVAL0);
+ __raw_writel(1, PIT_TCTRL0);
+
+ lastinc = __raw_readl(PIT_LTMR64H);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned long now, diff;
+
+ now = __raw_readl(PIT_LTMR64H);
+ diff = -(now - lastinc);
+ ltmstamp += diff;
+ while (ltmstamp > 100) {
+ timestamp++;
+ ltmstamp -= 100;
+ }
+ lastinc = now;
+
+ return timestamp - base;
+}
+
+/* delay x useconds AND preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+ ulong nsecs, tmp;
+
+ /*
+ * nsecs conversion = (1/ipg_clk) * 10^9
+ * equivalent to 1000 / (ipg_clk / 10^6)
+ */
+ if (usec < 5)
+ usec = 10;
+
+ nsecs = gd->ipg_clk / 1000000;
+ nsecs = 1000 / nsecs;
+
+ /* 1 us per ticks = 1000 ns / nsecs = cycles time */
+ while (usec > 0) {
+ if (usec > 65000)
+ tmp = 65000;
+ else
+ tmp = usec;
+ usec = usec - tmp;
+
+ tmp = (tmp * 1000) / nsecs;
+
+ __raw_writel(tmp, PIT_LDVAL2);
+ __raw_writel(1, PIT_TCTRL2);
+
+ while ((__raw_readl(PIT_TFLG2) & 1) != 1)
+ ;
+ __raw_writel(0, PIT_TCTRL2);
+ __raw_writel(1, PIT_TFLG2);
+ }
+}
+#endif /* CONFIG_TMR_USEPIT */
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long long _usec2ticks(unsigned long long usec)
+{
+ return usec;
+}
+
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
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