diff options
| author | Ye Li <ye.li@nxp.com> | 2019-10-25 01:40:11 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2019-10-28 04:10:04 -0700 |
| commit | 6ad93180ed2388a3453b268d1f5982b63b334367 (patch) | |
| tree | 7ff6dee216a92eadee23bf92bae55b4cd9c550ac /arch | |
| parent | 70af44d36f9c28d24dce88447a4ad8eaaae5c441 (diff) | |
MLK-22851-4 imx8mm/imx8mn: Enable eMMC HS400ES and SD UHS mode on EVK
Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0
So we enable the HS400ES and UHS configs to enhance eMMC/SD access.
The change also needs to set usdhc clock to 400Mhz and update compatible
string to fsl,imx8mm-usdhc
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/fsl-imx8mm.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/dts/fsl-imx8mn.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 |
3 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/dts/fsl-imx8mm.dtsi b/arch/arm/dts/fsl-imx8mm.dtsi index 41c8df1b2f..35209e4e52 100644 --- a/arch/arm/dts/fsl-imx8mm.dtsi +++ b/arch/arm/dts/fsl-imx8mm.dtsi @@ -531,7 +531,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b40000 0x0 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_DUMMY>, @@ -547,7 +547,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b50000 0x0 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_DUMMY>, @@ -561,7 +561,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b60000 0x0 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_DUMMY>, diff --git a/arch/arm/dts/fsl-imx8mn.dtsi b/arch/arm/dts/fsl-imx8mn.dtsi index c1dc4caec3..69c99c76bd 100644 --- a/arch/arm/dts/fsl-imx8mn.dtsi +++ b/arch/arm/dts/fsl-imx8mn.dtsi @@ -496,7 +496,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b40000 0x0 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_DUMMY>, @@ -512,7 +512,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b50000 0x0 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_DUMMY>, @@ -526,7 +526,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x0 0x30b60000 0x0 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_DUMMY>, diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 0a67f4ac49..92fc8a700c 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -694,9 +694,9 @@ int clock_init() clock_enable(CCGR_USDHC2, 0); clock_enable(CCGR_USDHC3, 0); clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); - clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); - clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); - clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_set_target_val(USDHC3_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC1, 1); clock_enable(CCGR_USDHC2, 1); clock_enable(CCGR_USDHC3, 1); |