diff options
| author | Marek Vasut <marex@denx.de> | 2020-05-22 01:12:39 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-06-22 17:44:06 +0200 |
| commit | cb82ee25f76757ff07d3d42a10e3432af40e0a64 (patch) | |
| tree | ddcb8dd4a0abf35cd14cec6d6ccb53d4797e0869 /arch | |
| parent | fb0b862e81afd60ee788ac4c8edfddf034d6dd47 (diff) | |
ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7
The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/mx7-ddr.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7/ddr.c | 1 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h index 37aaee0ad7..bea5dd8ec5 100644 --- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h +++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h @@ -39,7 +39,9 @@ struct ddrc { u32 dramtmg8; /* 0x0120 */ u32 reserved7[0x17]; u32 zqctl0; /* 0x0180 */ - u32 reserved8[0x03]; + u32 zqctl1; /* 0x0184 */ + u32 zqctl2; /* 0x0188 */ + u32 zqstat; /* 0x018c */ u32 dfitmg0; /* 0x0190 */ u32 dfitmg1; /* 0x0194 */ u32 reserved9[0x02]; diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index d1e10a6788..45954ed1ed 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -74,6 +74,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5); writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8); writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0); + writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1); writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0); writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1); writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0); |