diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-11-20 17:19:10 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2013-11-20 17:19:10 +0100 |
| commit | 524884460ef40abe19617e9a2855d1f88a978af4 (patch) | |
| tree | da14a6b8e67bf2e1a64cbf901f6f7aa2be697783 /arch | |
| parent | 5d8d4f5ef931d6f0d0195f3961534690b3c2b08d (diff) | |
colibri_vf: implement module type auto detection
Implement module type (e.g. VF50 vs. VF61) auto detection based on L2
cache availability. Set specific ARM core clock (e.g. 400 vs. 500 MHz)
as well as Linux machine id number.
While at it actually use memargs instead of hard-coded mem= value.
While at it fix sdboot command if initially booting U-Boot from NAND by
doing an explicit mmc part 0.
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid-common/cpu.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid-common/speed.c | 7 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid/clock.c | 7 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/vybrid/lowlevel_init.S | 10 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 3 |
5 files changed, 29 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c b/arch/arm/cpu/armv7/vybrid-common/cpu.c index 865c01fc58..4c2dcfe0fa 100644 --- a/arch/arm/cpu/armv7/vybrid-common/cpu.c +++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c @@ -103,7 +103,11 @@ int print_cpuinfo(void) (cpurev & 0xFFF000) >> 12, (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, +#ifdef CONFIG_AUTO_DETECT_FREQUENCY + __raw_readl(MSCM_CP0CFG1)?500:400); +#else vybrid_get_clock(VYBRID_ARM_CLK) / 1000000); +#endif if (get_reset_cause() != NULL) printf("Reset cause: %s\n", get_reset_cause()); return 0; diff --git a/arch/arm/cpu/armv7/vybrid-common/speed.c b/arch/arm/cpu/armv7/vybrid-common/speed.c index df768b37e4..7983063479 100644 --- a/arch/arm/cpu/armv7/vybrid-common/speed.c +++ b/arch/arm/cpu/armv7/vybrid-common/speed.c @@ -33,7 +33,12 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { gd->bus_clk = 66000000; - gd->ipg_clk = 66000000; +#ifdef CONFIG_AUTO_DETECT_FREQUENCY + if (__raw_readl(MSCM_CP0CFG1)) + gd->ipg_clk = 83000000; + else +#endif + gd->ipg_clk = 66000000; #ifdef CONFIG_FSL_ESDHC gd->sdhc_clk = 132000000; #endif diff --git a/arch/arm/cpu/armv7/vybrid/clock.c b/arch/arm/cpu/armv7/vybrid/clock.c index eea6af0f57..190333943e 100644 --- a/arch/arm/cpu/armv7/vybrid/clock.c +++ b/arch/arm/cpu/armv7/vybrid/clock.c @@ -176,7 +176,12 @@ static u32 get_ipg_clk(void) return freq / div; #else - return 66000000; +#ifdef CONFIG_AUTO_DETECT_FREQUENCY + if (__raw_readl(MSCM_CP0CFG1)) + return 83000000; + else +#endif + return 66000000; #endif } diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S index 8c22e3c365..630e4a8efe 100644 --- a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S +++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S @@ -132,7 +132,17 @@ ldr r1, =CONFIG_SYS_CLKCTRL_CCR str r1, [r0, #CLKCTL_CCR] +#ifdef CONFIG_AUTO_DETECT_FREQUENCY + /* check for L2 cache */ + ldr r2, =MSCM_BASE_ADDR + ldr r1, [r2, #MSCM_CP0CFG1_OFFSET] + cmp r1, #0x0 + ldr r1, =CONFIG_SYS_CLKCTRL_CCSR_400 + /* use 500 MHz if L2 cache present (Colibri VF61) */ + ldrne r1, =CONFIG_SYS_CLKCTRL_CCSR_500 +#else /* CONFIG_AUTO_DETECT_FREQUENCY */ ldr r1, =CONFIG_SYS_CLKCTRL_CCSR +#endif /* CONFIG_AUTO_DETECT_FREQUENCY */ str r1, [r0, #CLKCTL_CCSR] ldr r1, =CONFIG_SYS_CLKCTRL_CACRR diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h index d1647f0c18..19ab3731c0 100644 --- a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h +++ b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h @@ -103,6 +103,9 @@ #define MACNET0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) #define MACNET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) +#define MSCM_CP0CFG1_OFFSET 0x14 +#define MSCM_CP0CFG1 (MSCM_BASE_ADDR + MSCM_CP0CFG1_OFFSET) + /* WEIM CSnGCR1 */ #define CSEN 1 #define SWR (1 << 1) |