diff options
| author | Bryan Brattlof <bb@ti.com> | 2024-02-15 10:52:34 -0600 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2024-03-21 14:26:33 +0000 |
| commit | 99c22575231e465130191745e169720ce1a351c2 (patch) | |
| tree | 17af3cbab632613b732b6bec92ecde403dbe7261 | |
| parent | 8d06e27165251ddaa31bb49386559c979299d462 (diff) | |
arm: dts: k3-am62x-ddr: update to latest output from emif tool
The output from the emif tool hasn't changes in a long while however
there are some differences. Update to these latest settings.
Signed-off-by: Bryan Brattlof <bb@ti.com>
| -rw-r--r-- | arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi index d92e3ce048..b5f0e40c16 100644 --- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60 - * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time) + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07 + * Tue Feb 28 2023 14:47:40 GMT-0600 (Central Standard Time) * DDR Type: DDR4 * Frequency = 800MHz (1600MTs) * Density: 16Gb @@ -334,7 +334,7 @@ #define DDRSS_CTL_318_DATA 0x3FFF0000 #define DDRSS_CTL_319_DATA 0x000FFF00 #define DDRSS_CTL_320_DATA 0xFFFFFFFF -#define DDRSS_CTL_321_DATA 0x000FFF00 +#define DDRSS_CTL_321_DATA 0x00FFFF00 #define DDRSS_CTL_322_DATA 0x0A000000 #define DDRSS_CTL_323_DATA 0x0001FFFF #define DDRSS_CTL_324_DATA 0x01010101 @@ -901,7 +901,7 @@ #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 #define DDRSS_PHY_119_DATA 0x01000080 -#define DDRSS_PHY_120_DATA 0x01A00000 +#define DDRSS_PHY_120_DATA 0x01000000 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 #define DDRSS_PHY_123_DATA 0x00080200 @@ -1157,7 +1157,7 @@ #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 #define DDRSS_PHY_375_DATA 0x01000080 -#define DDRSS_PHY_376_DATA 0x01A00000 +#define DDRSS_PHY_376_DATA 0x01000000 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 #define DDRSS_PHY_379_DATA 0x00080200 @@ -2152,7 +2152,7 @@ #define DDRSS_PHY_1368_DATA 0x00000002 #define DDRSS_PHY_1369_DATA 0x00000100 #define DDRSS_PHY_1370_DATA 0x00000000 -#define DDRSS_PHY_1371_DATA 0x0001F7C0 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 #define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 |