diff options
| author | Igor Opaniuk <igor.opaniuk@toradex.com> | 2020-10-19 09:44:28 +0300 |
|---|---|---|
| committer | Igor Opaniuk <igor.opaniuk@toradex.com> | 2020-10-19 09:44:28 +0300 |
| commit | 34c25550c7fcd367b39cacdea2af9e47f412f8bc (patch) | |
| tree | a345672340cd4f82075257da8ed1c66dd8538338 | |
| parent | 1d1f59d2ec5dce4a5791450eda96dee9641bb642 (diff) | |
ARM: dts: fsl-imx8qxp-colibri: drop u-boot properties from generic dts
Drop u-boot specific from generic device tree.
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| -rw-r--r-- | arch/arm/dts/fsl-imx8qxp-colibri.dts | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri.dts b/arch/arm/dts/fsl-imx8qxp-colibri.dts index b2b997e593..9569ae8a6d 100644 --- a/arch/arm/dts/fsl-imx8qxp-colibri.dts +++ b/arch/arm/dts/fsl-imx8qxp-colibri.dts @@ -36,12 +36,10 @@ }; &iomuxc { - u-boot,dm-pre-proper; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>; colibri-imx8x { - u-boot,dm-pre-proper; pinctrl_lpuart0: lpuart0grp { fsl,pins = < SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 @@ -166,7 +164,6 @@ }; pinctrl_usdhc1: usdhc1grp { - u-boot,dm-pre-proper; fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 @@ -184,7 +181,6 @@ }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - u-boot,dm-pre-proper; fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 @@ -202,7 +198,6 @@ }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - u-boot,dm-pre-proper; fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 @@ -220,14 +215,12 @@ }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { - u-boot,dm-pre-proper; fsl,pins = < SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 >; }; pinctrl_usdhc2: usdhc2grp { - u-boot,dm-pre-proper; fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 @@ -240,7 +233,6 @@ }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - u-boot,dm-pre-proper; fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 @@ -253,7 +245,6 @@ }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - u-boot,dm-pre-proper; fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 @@ -281,10 +272,6 @@ }; }; -&A35_0 { - u-boot,dm-pre-reloc; -}; - &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; |