board: toradex: up-port verdin imx8mm module support

This patch introduces changes on top of existing Verdin iMX8MM support in
the mainline U-Boot v2020.04.

Some patches were already upstreamed, some were squashed and included
into this commit:

78e80d3f ("board: toradex: add verdin imx8mm 2gb wb it v1.0a module support")
a6c18891 ("verdin-imx8mm: lpddr4_timing.c: intial lpddr4 calibration data")
b16da3d6 ("verdin-imx8mm: fix usb_1 device aka peripheral operation")
6451e680 ("verdin-imx8: do not undef configs configured using Kconfig")
d5382436 ("fsl-imx8mm-verdin.dts: remove fsl,rgmii_rxc_dly et. al.")
c24fe844 ("fsl-imx8mm-verdin.dts: fix eth phy power up")
b07ae5f3 ("verdin-imx8mm.c: set eth phy skew")
4eb91e6e ("tdx-cfg-block: adjust verdin naming")
569703d4 ("verdin-imx8mm: sync with EVK board")
8c8b56a5 ("tdx-cfg-block: add proper defines for other Verdin SKUs")

Relates-to: ELB-2771
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>

6 files changed, 1320 insertions, 874 deletions

diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index e60b9faee4..80d45e5daa 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -82,11 +82,11 @@
 	u-boot,dm-spl;
 };
 
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+&{/soc@0/bus@30800000/i2c@30a20000/bd71837@4b} {
 	u-boot,dm-spl;
 };
 
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+&{/soc@0/bus@30800000/i2c@30a20000/bd71837@4b/regulators} {
 	u-boot,dm-spl;
 };
 
diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts
index b86f46e03e..d8ccb2b9e5 100644
--- a/arch/arm/dts/imx8mm-verdin.dts
+++ b/arch/arm/dts/imx8mm-verdin.dts
@@ -1,89 +1,101 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2020 Toradex
+ * Copyright 2019 Toradex
  */
 
 /dts-v1/;
 
-#include <dt-bindings/usb/pd.h>
 #include "imx8mm.dtsi"
 
 / {
-	model = "Toradex Verdin iMX8M Mini Quad/DualLite";
+	model = "Toradex Verdin iMX8MM";
 	compatible = "toradex,verdin-imx8mm", "fsl,imx8mm";
 
 	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
 		stdout-path = &uart1;
 	};
 
-	/* fixed clock dedicated to SPI CAN controller */
-	clk20m: oscillator {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <20000000>;
+	aliases {
+		eeprom0 = &eeprom_module;
+		eeprom1 = &eeprom_carrier;
+		eeprom2 = &eeprom_mipi_dsi;
 	};
 
-	reg_ethphy: regulator-ethphy {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
-		off-on-delay = <500000>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_eth>;
-		regulator-boot-on;
-		regulator-max-microvolt = <3300000>;
-		regulator-min-microvolt = <3300000>;
-		regulator-name = "V3.3_ETH";
-		startup-delay-us = <200000>;
-	};
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
 
-	reg_usb_otg1_vbus: regulator-usb-otg1 {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		/* Verdin USB1_EN */
-		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usb1_en>;
-		regulator-name = "usb_otg1_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
+		reg_ethphy: regulator-ethphy {
+			compatible = "regulator-fixed";
+			enable-active-high;
+			gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+			off-on-delay = <500000>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_reg_eth>;
+			regulator-boot-on;
+			regulator-name = "V3.3_ETH";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			startup-delay-us = <200000>;
+		};
 
-	reg_usb_otg2_vbus: regulator-usb-otg2 {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		/* Verdin USB2_EN */
-		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usb2_en>;
-		regulator-name = "usb_otg2_vbus";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-	};
+		reg_usdhc2_vmmc: regulator-usdhc2 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
+			regulator-name = "V3.3_SD";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
+			startup-delay-us = <2000>;
+			enable-active-high;
+		};
 
-	reg_usdhc2_vmmc: regulator-usdhc2 {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
-		regulator-name = "V3.3_SD";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <2000>;
+		reg_usb_otg1_vbus: regulator-usb-otg1 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_reg_usb1_en>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			/* Verdin USB1_EN */
+			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		reg_usb_otg2_vbus: regulator-usb-otg2 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_reg_usb2_en>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			/* Verdin USB2_EN */
+			gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		};
 	};
 
-	reg_wifi_en: regulator-wifi-en {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
-		regulator-name = "V3.3_WI-FI";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		startup-delay-us = <2000>;
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "imx8mm-wm8904";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&dailink_master>;
+		simple-audio-card,frame-master = <&dailink_master>;
+		/*simple-audio-card,mclk-fs = <1>;*/
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+		};
+
+		dailink_master: simple-audio-card,codec {
+			sound-dai = <&wm8904_1a>;
+//			clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
+		};
 	};
+
 };
 
 &A53_0 {
@@ -95,70 +107,13 @@
 	assigned-clock-rates = <786432000>, <722534400>;
 };
 
-/* Verdin SPI_1 */
-&ecspi2 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi2>;
-	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
-	status = "okay";
-
-	spidev20: spidev@0 {
-		compatible = "toradex,evalspi";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-		status = "okay";
-	};
-};
-
-/* On-module CAN controller 1 & 2 */
-&ecspi3 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>,
-		   <&gpio1 5 GPIO_ACTIVE_LOW>;
-	/* This property is required, even if marked as obsolete in the doku */
-	fsl,spi-num-chipselects = <2>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi3>;
-	status = "okay";
-
-	can1: can@0 {
-		compatible = "microchip,mcp2517fd";
-		clocks = <&clk20m>;
-		gpio-controller;
-		interrupt-parent = <&gpio1>;
-		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
-		microchip,clock-allways-on;
-		microchip,clock-out-div = <1>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_can1_int>;
-		reg = <0>;
-		spi-max-frequency = <2000000>;
-	};
-
-	can2: can@1 {
-		compatible = "microchip,mcp2517fd";
-		clocks = <&clk20m>;
-		gpio-controller;
-		interrupt-parent = <&gpio1>;
-		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_can2_int>;
-		reg = <1>;
-		spi-max-frequency = <2000000>;
-	};
-};
-
 &fec1 {
-	fsl,magic-packet;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
 	phy-handle = <&ethphy0>;
 	phy-mode = "rgmii";
 	phy-supply = <&reg_ethphy>;
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_fec1>;
-	pinctrl-1 = <&pinctrl_fec1_sleep>;
+	fsl,magic-packet;
 	status = "okay";
 
 	mdio {
@@ -169,166 +124,165 @@
 			compatible = "ethernet-phy-ieee802.3-c22";
 			interrupt-parent = <&gpio1>;
 			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
-			micrel,led-mode = <0>;
 			reg = <7>;
+			micrel,led-mode = <0>;
 		};
 	};
 };
 
-&gpio4 {
-	/*
-	 * The SE050 security element may be driven via I2C from user space.
-	 * The element itself is enabled here as it has no kernel driver.
-	 */
-	se050_ena {
-		gpio-hog;
-		gpios = <19 GPIO_ACTIVE_HIGH>;
-		line-name = "SE050_ENABLE";
-		output-high;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_se050_ena>;
-	};
-};
-
-/* On-module I2C */
 &i2c1 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	status = "okay";
 
-	pmic@4b {
+	pmic: bd71837@4b {
+		reg = <0x4b>;
 		compatible = "rohm,bd71840", "rohm,bd71837";
-		bd71837,pmic-buck2-uses-i2c-dvs;
-		bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
-		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
 		/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
 		pinctrl-0 = <&pinctrl_pmic>;
-		reg = <0x4b>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
 
 		gpo {
 			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
 		};
 
 		regulators {
-			buck1_reg: BUCK1 {
-				regulator-always-on;
-				regulator-boot-on;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			bd71837,pmic-buck2-uses-i2c-dvs;
+			bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
 				regulator-compatible = "buck1";
-				regulator-max-microvolt = <1300000>;
 				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
 				regulator-ramp-delay = <1250>;
 			};
 
-			buck2_reg: BUCK2 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck2_reg: regulator@1 {
+				reg = <1>;
 				regulator-compatible = "buck2";
-				regulator-max-microvolt = <1300000>;
 				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
 				regulator-ramp-delay = <1250>;
 			};
 
-			buck5_reg: BUCK5 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck5_reg: regulator@4 {
+				reg = <4>;
 				regulator-compatible = "buck5";
-				regulator-max-microvolt = <1350000>;
 				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			buck6_reg: BUCK6 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck6_reg: regulator@5 {
+				reg = <5>;
 				regulator-compatible = "buck6";
-				regulator-max-microvolt = <3300000>;
 				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			buck7_reg: BUCK7 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck7_reg: regulator@6 {
+				reg = <6>;
 				regulator-compatible = "buck7";
-				regulator-max-microvolt = <1995000>;
 				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			buck8_reg: BUCK8 {
-				regulator-always-on;
-				regulator-boot-on;
+			buck8_reg: regulator@7 {
+				reg = <7>;
 				regulator-compatible = "buck8";
-				regulator-max-microvolt = <1400000>;
 				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			ldo1_reg: LDO1 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo1_reg: regulator@8 {
+				reg = <8>;
 				regulator-compatible = "ldo1";
-				regulator-max-microvolt = <3300000>;
 				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			ldo2_reg: LDO2 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo2_reg: regulator@9 {
+				reg = <9>;
 				regulator-compatible = "ldo2";
-				regulator-max-microvolt = <900000>;
 				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			ldo3_reg: LDO3 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo3_reg: regulator@10 {
+				reg = <10>;
 				regulator-compatible = "ldo3";
-				regulator-max-microvolt = <3300000>;
 				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			ldo4_reg: LDO4 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo4_reg: regulator@11 {
+				reg = <11>;
 				regulator-compatible = "ldo4";
-				regulator-max-microvolt = <1800000>;
 				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 
-			ldo5_reg: LDO5 {
+			ldo5_reg: regulator@12 {
+				reg = <12>;
 				regulator-compatible = "ldo5";
-				regulator-max-microvolt = <3300000>;
 				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
 			};
 
-			ldo6_reg: LDO6 {
-				regulator-always-on;
-				regulator-boot-on;
+			ldo6_reg: regulator@13 {
+				reg = <13>;
 				regulator-compatible = "ldo6";
-				regulator-max-microvolt = <1800000>;
 				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
 			};
 		};
 	};
 
 	/* Epson RX8130 real time clock on carrier board */
-	rtc@32 {
+	rtc: rx8130@32 {
 		compatible = "epson,rx8130";
 		reg = <0x32>;
 	};
 
-	adc@34 {
+	adc: max11607@34 {
 		compatible = "maxim,max11607";
 		reg = <0x34>;
 		vcc-supply = <&ldo5_reg>;
 	};
 
-	eeprom@50 {
-		compatible = "st,24c02";
+	eeprom_module: eeprom@50 {
+		compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 		pagesize = <16>;
 		reg = <0x50>;
 	};
 };
 
-/* Verdin I2C_2_DSI */
 &i2c2 {
 	clock-frequency = <10000>;
 	pinctrl-names = "default";
@@ -336,9 +290,6 @@
 	status = "okay";
 };
 
-/* Verdin I2C_3_HDMI N/A */
-
-/* Verdin I2C_4_CSI */
 &i2c3 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -346,7 +297,6 @@
 	status = "okay";
 };
 
-/* Verdin I2C_1 */
 &i2c4 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -354,77 +304,96 @@
 	status = "okay";
 
 	/* Audio Codec */
-	wm8904_1a: codec@1a {
+	wm8904_1a: wm8904@1a {
 		compatible = "wlf,wm8904";
 		#sound-dai-cells = <0>;
+		reg = <0x1a>;
 		clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
 		clock-names = "mclk";
-		reg = <0x1a>;
 	};
 
 	gpio_expander_21: gpio-expander@21 {
 		compatible = "nxp,pcal6416";
-		#gpio-cells = <2>;
 		gpio-controller;
+		#gpio-cells = <2>;
 		reg = <0x21>;
 	};
 
 	/* Current measurement into module VCC */
-	hwmon@40 {
+	ina219@40 {
 		compatible = "ti,ina219";
 		reg = <0x40>;
 		shunt-resistor = <10000>;
 		status = "okay";
 	};
 
+	/* MIPI-DSI to HDMI adapter */
+	lt8912@48 {
+		compatible = "lontium,lt8912";
+		ddc-i2c-bus = <&i2c2>;
+		hpd-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_hpd>, <&pinctrl_gpio1>,
+			    <&pinctrl_gpio2>;
+		reg = <0x48>;
+
+		port {
+			lt8912_1_in: endpoint {
+				remote-endpoint = <&mipi_dsi_bridge1_out>;
+			};
+		};
+	};
+
 	/* EEPROM on MIPI-DSI to HDMI adapter */
-	eeprom_50: eeprom@50 {
-		compatible = "st,24c02";
+	eeprom_mipi_dsi: eeprom@50 {
+		compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 		pagesize = <16>;
 		reg = <0x50>;
 	};
 
 	/* EEPROM on Verdin Development board */
-	eeprom_57: eeprom@57 {
-		compatible = "st,24c02";
+	eeprom_carrier: eeprom@57 {
+		compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
 		pagesize = <16>;
 		reg = <0x57>;
 	};
 };
 
-/* Verdin PWM_3_DSI */
-&pwm1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_1>;
-	#pwm-cells = <3>;
+&lcdif {
 	status = "okay";
 };
 
-/* Verdin PWM_1 */
-&pwm2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_2>;
-	#pwm-cells = <3>;
+&mipi_dsi {
 	status = "okay";
+
+	port@1 {
+		mipi_dsi_bridge1_out: endpoint {
+			remote-endpoint = <&lt8912_1_in>;
+		};
+	};
 };
 
-/* Verdin PWM_2 */
-&pwm3 {
+/* VERDIN I2S_1 */
+&sai2 {
+	#sound-dai-cells = <0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_3>;
-	#pwm-cells = <3>;
+	pinctrl-0 = <&pinctrl_sai2>;
+	assigned-clocks = <&clk IMX8MM_CLK_SAI2_SRC>,
+			<&clk IMX8MM_CLK_SAI2_DIV>;
+	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
+	assigned-clock-rates = <0>, <24576000>;
 	status = "okay";
 };
 
-/* Verdin UART_3, Console/Debug UART */
+/* Verdin UART3 */
 &uart1 {
-	fsl,uart-has-rtscts;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
 	status = "okay";
 };
 
-/* Verdin UART_1 */
+/* Verdin UART1 */
 &uart2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
@@ -432,7 +401,7 @@
 	status = "okay";
 };
 
-/* Verdin UART_2 */
+/* Verdin UART2 */
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart3>;
@@ -440,35 +409,6 @@
 	status = "okay";
 };
 
-/* Verdin UART_4 */
-/*
- * resource allocated to M4 by default, must not be accessed from A-35 or you
- * get an OOPS
- */
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "disabled";
-};
-
-/* Verdin USB_1 */
-&usbotg1 {
-	dr_mode = "otg";
-	picophy,dc-vol-level-adjust = <7>;
-	picophy,pre-emp-curr-control = <3>;
-	vbus-supply = <&reg_usb_otg1_vbus>;
-	status = "okay";
-};
-
-/* Verdin USB_2 */
-&usbotg2 {
-	dr_mode = "host";
-	picophy,dc-vol-level-adjust = <7>;
-	picophy,pre-emp-curr-control = <3>;
-	vbus-supply = <&reg_usb_otg2_vbus>;
-	status = "okay";
-};
-
 /* On-module eMMC */
 &usdhc1 {
 	bus-width = <8>;
@@ -483,523 +423,450 @@
 	/* TODO Strobe */
 };
 
-/* Verdin SD_1 */
+/* Verdin SDIO 1 */
 &usdhc2 {
-	bus-width = <4>;
-	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
 	vmmc-supply = <&reg_usdhc2_vmmc>;
 	status = "okay";
 };
 
-/* On-module Wi-Fi */
-&usdhc3 {
-	bus-width = <4>;
-	non-removable;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
-	vmmc-supply = <&reg_wifi_en>;
+&usbotg1 {
+	dr_mode = "peripheral";
+	picophy,pre-emp-curr-control = <3>;
+	picophy,dc-vol-level-adjust = <7>;
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	picophy,pre-emp-curr-control = <3>;
+	picophy,dc-vol-level-adjust = <7>;
+	vbus-supply = <&reg_usb_otg2_vbus>;
 	status = "okay";
 };
 
 &wdog1 {
-	fsl,ext-reset-output;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
 	status = "okay";
 };
 
 &iomuxc {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio1>, <&pinctrl_gpio2>,
-		    <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>,
-		    <&pinctrl_gpio6>, <&pinctrl_gpio7>, <&pinctrl_gpio8>,
-		    <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>,
-		    <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hpd>;
-
-	pinctrl_can1_int: can1intgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x1c4
-		>;
-	};
-
-	pinctrl_can2_int: can2intgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x1c4
-		>;
-	};
-
-	pinctrl_ctrl_force_off_moci: ctrlforceoffgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x1c4		/* SODIMM 250 */
-		>;
-	};
-
-	pinctrl_dsi_bkl_en: dsi_bkl_en {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3	0x1c4		/* SODIMM 21 */
-		>;
-	};
-
-	pinctrl_ecspi2: ecspi2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x1c4		/* SODIMM 198 */
-			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x4		/* SODIMM 200 */
-			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x4		/* SODIMM 196 */
-			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x1c4		/* SODIMM 202 */
-		>;
-	};
-
-	pinctrl_ecspi3: ecspi3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x1c4
-			MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK	0x4
-			MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI	0x4
-			MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO	0x1c4
-			MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25	0x1c4
-		>;
-	};
-
-	pinctrl_fec1: fec1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
-			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
-			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
-			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
-			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c4
-		>;
-	};
-
-	pinctrl_fec1_sleep: fec1-sleepgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
-			MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f
-			MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f
-			MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19		0x1f
-			MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18		0x1f
-			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23		0x1f
-			MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x1f
-			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x184
-		>;
-	};
-
-	pinctrl_flexspi0: flexspi0grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x1c2		/* SODIMM 52 */
-			MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82		/* SODIMM 54 */
-			MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B	0x82		/* SODIMM 64 */
-			MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82		/* SODIMM 56 */
-			MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82		/* SODIMM 58 */
-			MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82		/* SODIMM 60 */
-			MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82		/* SODIMM 62 */
-			MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS	0x82		/* SODIMM 66 */
-		>;
-	};
+	pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>,
+		    <&pinctrl_gpio4>, <&pinctrl_gpio5>, <&pinctrl_gpio6>,
+		    <&pinctrl_gpio7>, <&pinctrl_gpio8>, <&pinctrl_se050_ena>;
+
+	imx8mm-verdin {
+		pinctrl_ctrl_force_off_moci: forceoffgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x1c4		/* SODIMM 250 */
+			>;
+		};
 
-	/* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
-	pinctrl_gpio1: gpio1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x184		/* SODIMM 206 */
-		>;
-	};
+		pinctrl_can1_int: can1intgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x1c4
+			>;
+		};
 
-	pinctrl_gpio2: gpio2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x184		/* SODIMM 208 */
-		>;
-	};
+		pinctrl_can2_int: can2intgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x1c4
+			>;
+		};
 
-	pinctrl_gpio3: gpio3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26	0x184		/* SODIMM 210 */
-		>;
-	};
+		pinctrl_ecspi2: ecspi2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x4		/* SODIMM 196 */
+				MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x4		/* SODIMM 200 */
+				MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x1c4		/* SODIMM 198 */
+				MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x1c4		/* SODIMM 202 */
+			>;
+		};
 
-	pinctrl_gpio4: gpio4grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27	0x184		/* SODIMM 212 */
-		>;
-	};
+		pinctrl_ecspi3: ecspi3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK	0x4
+				MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI	0x4
+				MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO	0x1c4
+				MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25	0x1c4
+				MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x1c4
+			>;
+		};
 
-	pinctrl_gpio5: gpio5grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x184		/* SODIMM 216 */
-		>;
-	};
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
+				MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+				MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+				MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+				MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+				MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+				MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c4
+			>;
+		};
 
-	pinctrl_gpio6: gpio6grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x184		/* SODIMM 218 */
-		>;
-	};
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x1c2		/* SODIMM 52 */
+				MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82		/* SODIMM 54 */
+				MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B	0x82		/* SODIMM 64 */
+				MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS	0x82		/* SODIMM 66 */
+				MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82		/* SODIMM 56 */
+				MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82		/* SODIMM 58 */
+				MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82		/* SODIMM 60 */
+				MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82		/* SODIMM 62 */
+			>;
+		};
 
-	pinctrl_gpio7: gpio7grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x184		/* SODIMM 220 */
-		>;
-	};
+		/* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */
+		pinctrl_gpio_hpd: gpiohpdgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15	0x184		/* SODIMM 17 */
+			>;
+		};
 
-	pinctrl_gpio8: gpio8grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x184		/* SODIMM 222 */
-		>;
-	};
+		/* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
+		pinctrl_gpio1: gpio1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x184		/* SODIMM 206 */
+			>;
+		};
 
-	pinctrl_gpio_hog1: gpiohog1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x1c4		/* SODIMM 88 */
-			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x1c4		/* SODIMM 90 */
-			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x1c4		/* SODIMM 92 */
-			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x1c4		/* SODIMM 94 */
-			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x1c4		/* SODIMM 96 */
-			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x1c4		/* SODIMM 100 */
-			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x1c4		/* SODIMM 102 */
-			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x1c4		/* SODIMM 104 */
-			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x1c4		/* SODIMM 106 */
-			MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13	0x1c4		/* SODIMM 108 */
-			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x1c4		/* SODIMM 112 */
-			MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15	0x1c4		/* SODIMM 114 */
-			MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16	0x1c4		/* SODIMM 116 */
-			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18	0x1c4		/* SODIMM 118 */
-			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x1c4		/* SODIMM 120 */
-		>;
-	};
+		pinctrl_gpio2: gpio2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x184		/* SODIMM 208 */
+			>;
+		};
 
-	pinctrl_gpio_hog2: gpiohog2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2	0x1c4		/* SODIMM 91 */
-		>;
-	};
+		pinctrl_gpio3: gpio3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26	0x184		/* SODIMM 210 */
+			>;
+		};
 
-	pinctrl_gpio_hog3: gpiohog3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x1c4		/* SODIMM 157 */
-			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4		/* SODIMM 187 */
-		>;
-	};
+		pinctrl_gpio4: gpio4grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27	0x184		/* SODIMM 212 */
+			>;
+		};
 
-	/* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */
-	pinctrl_gpio_hpd: gpiohpdgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15	0x184		/* SODIMM 17 */
-		>;
-	};
+		pinctrl_gpio5: gpio5grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x184		/* SODIMM 216 */
+			>;
+		};
 
-	/* On-module I2C */
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c6
-			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c6
-		>;
-	};
+		pinctrl_gpio6: gpio6grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x184		/* SODIMM 218 */
+			>;
+		};
 
-	/* Verdin I2C_4_CSI */
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c6	/* SODIMM 55 */
-			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c6	/* SODIMM 53 */
-		>;
-	};
+		pinctrl_gpio7: gpio7grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x184		/* SODIMM 220 */
+			>;
+		};
 
-	/* Verdin I2C_2_DSI */
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c6	/* SODIMM 95 */
-			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c6	/* SODIMM 93 */
-		>;
-	};
+		pinctrl_gpio8: gpio8grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x184		/* SODIMM 222 */
+			>;
+		};
 
-	/* Verdin I2C_1 */
-	pinctrl_i2c4: i2c4grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c6	/* SODIMM 14 */
-			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c6	/* SODIMM 12 */
-		>;
-	};
+		/* On Module I2C */
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c6
+				MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c6
+			>;
+		};
 
-	pinctrl_pcie0: pcie0grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x6		/* SODIMM 244 */
-			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x6		/* PMIC_EN_PCIe_CLK */
-		>;
-	};
+		/* Verdin I2C_4_CSI */
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c6	/* SODIMM 55 */
+				MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c6	/* SODIMM 53 */
+			>;
+		};
 
-	pinctrl_pmic: pmicirqgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
-		>;
-	};
+		/* Verdin I2C_2_DSI */
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c6	/* SODIMM 95 */
+				MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c6	/* SODIMM 93 */
+			>;
+		};
 
-	pinctrl_pwm_1: pwm1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6		/* SODIMM 19 */
-		>;
-	};
+		/* Verdin I2C_1 */
+		pinctrl_i2c4: i2c4grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c6	/* SODIMM 14 */
+				MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c6	/* SODIMM 12 */
+			>;
+		};
 
-	pinctrl_pwm_2: pwm2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT		0x6		/* SODIMM 15 */
-		>;
-	};
+		pinctrl_pcie0: pcie0grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x6		/* SODIMM 244 */
+				MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x6
+			>;
+		};
 
-	pinctrl_pwm_3: pwm3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT		0x6		/* SODIMM 16 */
-		>;
-	};
+		pinctrl_pmic: pmicirq {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
+			>;
+		};
 
-	pinctrl_reg_eth: regethgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SD2_WP_GPIO2_IO20		0x184
-		>;
-	};
+		pinctrl_reg_eth: regethgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_WP_GPIO2_IO20		0x184
+			>;
+		};
 
-	pinctrl_reg_usb1_en: regusb1engrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x184		/* SODIMM 155 */
-		>;
-	};
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6		/* SODIMM 32 */
+				MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6		/* SODIMM 30 */
+				MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6		/* SODIMM 38 */
+				MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6		/* SODIMM 36 */
+				MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6		/* SODIMM 34 */
+			>;
+		};
 
-	pinctrl_reg_usb2_en: regusb2engrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x184		/* SODIMM 185 */
-		>;
-	};
+		pinctrl_sai5: sai5grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0	0xd6		/* SODIMM 48 */
+				MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC	0xd6		/* SODIMM 44 */
+				MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK	0xd6		/* SODIMM 42 */
+				MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0	0xd6		/* SODIMM 46 */
+			>;
+		};
 
-	pinctrl_sai2: sai2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6		/* SODIMM 38 */
-			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6		/* SODIMM 36 */
-			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6		/* SODIMM 30 */
-			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6		/* SODIMM 34 */
-			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6		/* SODIMM 32 */
-		>;
-	};
+		pinctrl_se050_ena: se050enagrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x184
+			>;
+		};
 
-	pinctrl_sai5: sai5grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0	0xd6		/* SODIMM 48 */
-			MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC	0xd6		/* SODIMM 44 */
-			MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK	0xd6		/* SODIMM 42 */
-			MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0	0xd6		/* SODIMM 46 */
-		>;
-	};
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI2_RXFS_UART1_TX	0x1c4		/* SODIMM 149 */
+				MX8MM_IOMUXC_SAI2_RXC_UART1_RX		0x1c4		/* SODIMM 147 */
+			>;
+		};
 
-	pinctrl_se050_ena: se050enagrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19	0x184
-		>;
-	};
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x1c4		/* SODIMM 129 */
+				MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x1c4		/* SODIMM 131 */
+				MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x1c4		/* SODIMM 133 */
+				MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x1c4		/* SODIMM 135 */
+			>;
+		};
 
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX	0x1c4		/* SODIMM 147 */
-			MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX	0x1c4		/* SODIMM 149 */
-		>;
-	};
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x1c4	/* SODIMM 137 */
+				MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x1c4	/* SODIMM 139 */
+				MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x1c4	/* SODIMM 141 */
+				MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x1c4	/* SODIMM 143 */
+			>;
+		};
 
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x1c4		/* SODIMM 133 */
-			MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x1c4		/* SODIMM 135 */
-			MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x1c4		/* SODIMM 131 */
-			MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x1c4		/* SODIMM 129 */
-		>;
-	};
+		pinctrl_uart4: uart4grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x1c4		/* SODIMM 151 */
+				MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x1c4		/* SODIMM 153 */
+			>;
+		};
 
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x1c4	/* SODIMM 141 */
-			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x1c4	/* SODIMM 139 */
-			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x1c4	/* SODIMM 137 */
-			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x1c4	/* SODIMM 143 */
-		>;
-	};
+		pinctrl_reg_usb1_en: regusb1en {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x184		/* SODIMM 155 */
+			>;
+		};
 
-	pinctrl_uart4: uart4grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x1c4		/* SODIMM 151 */
-			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x1c4		/* SODIMM 153 */
-		>;
-	};
+		pinctrl_reg_usb2_en: regusb2en {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x184		/* SODIMM 185 */
+			>;
+		};
 
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
-			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
-			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
-			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
-			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
-			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
-			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0
-			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0
-			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0
-			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0
-			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x190
-		>;
-	};
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK	0x190
+				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD	0x1d0
+				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
+				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
+				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
+				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
+				MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d0
+				MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d0
+				MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d0
+				MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d0
+				MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x190
+			>;
+		};
 
-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-		fsl,pins = <
-			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
-			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
-			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
-			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
-			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
-			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
-			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4
-			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4
-			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4
-			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4
-			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x194
-		>;
-	};
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK	0x194
+				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD	0x1d4
+				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
+				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
+				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
+				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
+				MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d4
+				MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d4
+				MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d4
+				MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d4
+				MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x194
+			>;
+		};
 
-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-		fsl,pins = <
-			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
-			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
-			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
-			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
-			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
-			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
-			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6
-			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6
-			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6
-			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6
-			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x196
-		>;
-	};
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK	0x196
+				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD	0x1d6
+				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
+				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
+				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
+				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
+				MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4	0x1d6
+				MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5	0x1d6
+				MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6	0x1d6
+				MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7	0x1d6
+				MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x196
+			>;
+		};
 
-	pinctrl_usdhc2_cd: usdhc2cdgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4		/* SODIMM 84 */
-		>;
-	};
+		pinctrl_usdhc2_cd: usdhc2cdgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4		/* SODIMM 84 */
+			>;
+		};
 
-	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5		0x184		/* SODIMM 76 */
-		>;
-	};
+		pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5	0x184		/* SODIMM 76 */
+			>;
+		};
 
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190		/* SODIMM 78 */
-			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0		/* SODIMM 74 */
-			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0		/* SODIMM 80 */
-			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0		/* SODIMM 82 */
-			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0		/* SODIMM 70 */
-			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0		/* SODIMM 72 */
-		>;
-	};
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x190		/* SODIMM 78 */
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d0		/* SODIMM 74 */
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0		/* SODIMM 80 */
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0		/* SODIMM 82 */
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0		/* SODIMM 70 */
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0		/* SODIMM 72 */
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
-			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
-			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
-			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
-			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
-			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
-		>;
-	};
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x194
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d4
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
-			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
-			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
-			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
-			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
-			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
-		>;
-	};
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK	0x196
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD	0x1d6
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
 
-	pinctrl_usdhc3: usdhc3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
-			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
-			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
-			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
-			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
-			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
-		>;
-	};
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
+			>;
+		};
 
-	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
-			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
-			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
-			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
-			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
-			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
-		>;
-	};
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
+			>;
+		};
 
-	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
-			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
-			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
-			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
-			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
-			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
-		>;
-	};
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
+			>;
+		};
 
-	pinctrl_wdog: wdoggrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
-		>;
-	};
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
+			>;
+		};
 
-	pinctrl_wifi_ctrl: wifictrlgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x1c4		/* WIFI_WKUP_BT */
-			MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x1c4		/* WIFI_W_WKUP_HOST */
-			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x1c4		/* WIFI_WKUP_WLAN */
-		>;
-	};
+		pinctrl_wifi_ctrl: wifictrlgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x1c4		/* WIFI_WKUP_BT */
+				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x1c4		/* WIFI_WKUP_WLAN */
+				MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9	0x1c4		/* WIFI_W_WKUP_HOST */
+			>;
+		};
 
-	pinctrl_wifi_i2s: wifii2sgrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK	0xd6
-			MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0	0xd6
-			MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC	0xd6
-			MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0	0xd6
-		>;
-	};
+		pinctrl_wifi_pwr_en: wifipwrengrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x184		/* PMIC_EN_WIFI */
+			>;
+		};
 
-	pinctrl_wifi_pwr_en: wifipwrengrp {
-		fsl,pins = <
-			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x184		/* PMIC_EN_WIFI */
-		>;
+		pinctrl_wifi_i2s: wifii2sgrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK	0xd6
+				MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0	0xd6
+				MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC	0xd6
+				MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0	0xd6
+			>;
+		};
 	};
 };
diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c
index 55cde73e19..463378b610 100644
--- a/board/toradex/verdin-imx8mm/spl.c
+++ b/board/toradex/verdin-imx8mm/spl.c
@@ -4,22 +4,23 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/ddr.h>
 #include <asm/arch/imx8mm_pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <cpu_func.h>
-#include <dm/device.h>
-#include <dm/device-internal.h>
-#include <dm/uclass.h>
-#include <dm/uclass-internal.h>
-#include <hang.h>
-#include <power/bd71837.h>
+#include <asm/arch/ddr.h>
+
 #include <power/pmic.h>
-#include <spl.h>
+#include <power/bd71837.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,93 +47,183 @@ void spl_dram_init(void)
 	ddr_init(&dram_timing);
 }
 
-void spl_board_init(void)
-{
-	/* Serial download mode */
-	if (is_usb_boot()) {
-		puts("Back to ROM, SDP\n");
-		restore_boot_params();
-	}
-	puts("Normal Boot\n");
-}
-
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
-
-	return 0;
-}
-#endif
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
 
-#define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(3, 5)
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MM_PAD_SD1_CLK_USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_CMD_USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
 
-/* Verdin UART_3, Console/Debug UART */
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_GPIO3_IO5 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	/* esdhc_base, sdhc_clk, max_bus_width */
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
 };
 
-int board_early_init_f(void)
+int board_mmc_init(bd_t *bis)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1 (eMMC)
+	 * mmc1                    USDHC2 (SD card)
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			break;
+		case 1:
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "SD_1_PWR_EN");
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
 
-	set_wdog_reset(wdog);
+	return 0;
+}
 
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1; /* eMMC */
+		break;
+	case USDHC2_BASE_ADDR:
+		gpio_request(USDHC2_CD_GPIO, "SD_1_CD#");
+		gpio_direction_input(USDHC2_CD_GPIO);
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
 
-	return 0;
+	return 1;
 }
 
+#ifdef CONFIG_POWER
+#define I2C_PMIC	0
 int power_init_board(void)
 {
-	struct udevice *dev;
+	struct pmic *p;
 	int ret;
 
-	ret = pmic_get("pmic@4b", &dev);
-	if (ret == -ENODEV) {
-		puts("No pmic\n");
-		return 0;
-	}
-	if (ret != 0)
-		return ret;
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
 
 	/* decrease RESET key long push time from the default 10s to 10ms */
-	pmic_reg_write(dev, BD71837_PWRONCONFIG1, 0x0);
+	pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0);
 
 	/* unlock the PMIC regs */
-	pmic_reg_write(dev, BD71837_REGLOCK, 0x1);
+	pmic_reg_write(p, BD71837_REGLOCK, 0x1);
 
 	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
-	pmic_reg_write(dev, BD71837_BUCK1_VOLT_RUN, 0x0f);
+	pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f);
 
 	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
-	pmic_reg_write(dev, BD71837_BUCK5_VOLT, 0x83);
+	pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83);
 
 #ifndef CONFIG_IMX8M_LPDDR4
 	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
-	pmic_reg_write(dev, BD71837_BUCK8_VOLT, 0x28);
+	pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28);
 #endif
 
 	/* lock the PMIC regs */
-	pmic_reg_write(dev, BD71837_REGLOCK, 0x11);
+	pmic_reg_write(p, BD71837_REGLOCK, 0x11);
 
 	return 0;
 }
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
 
 void board_init_f(ulong dummy)
 {
-	struct udevice *dev;
 	int ret;
 
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
 	arch_cpu_init();
 
 	init_uart_clk(0);
@@ -143,25 +234,17 @@ void board_init_f(ulong dummy)
 
 	preloader_console_init();
 
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	ret = spl_early_init();
+	ret = spl_init();
 	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@30380000",
-					&dev);
-	if (ret < 0) {
-		printf("Failed to find clock node. Check device tree\n");
+		debug("spl_init() failed: %d\n", ret);
 		hang();
 	}
 
 	enable_tzc380();
 
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
 	power_init_board();
 
 	/* DDR initialization */
@@ -172,7 +255,7 @@ void board_init_f(ulong dummy)
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	puts("resetting ...\n");
+	puts ("resetting ...\n");
 
 	reset_cpu(WDOG1_BASE_ADDR);
 
diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
index 1e57efa3ec..4890984fa8 100644
--- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c
+++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c
@@ -4,35 +4,110 @@
  */
 
 #include <common.h>
-#include <asm/arch/clock.h>
 #include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
+#include <dm.h>
+#include <errno.h>
+#include <fsl_esdhc.h>
+#include <malloc.h>
+#include <micrel.h>
 #include <miiphy.h>
+#include <mmc.h>
 #include <netdev.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <spl.h>
+#include <usb.h>
+
+#include "../common/tdx-cfg-block.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if IS_ENABLED(CONFIG_FEC_MXC)
-static int setup_fec(void)
+#define UART_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+/* Verdin UART_3, Console/Debug UART */
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
 {
-	struct iomuxc_gpr_base_regs *gpr =
-		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 
-	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
-	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 
 	return 0;
 }
 
-int board_phy_config(struct phy_device *phydev)
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
 {
-	/* enable rgmii rxc skew and phy mode select to RGMII copper */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+	/* TODO */
+	return 0;
+}
+#endif
 
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+/*
+ * The PHY adds 1.2ns for the RXC and 0ns for TXC clock by default. The MAC
+ * and the layout don't add a skew between clock and data.
+ * Add 0.3ns for the RXC path and 0.96 + 0.42 ns (1.38 ns) for the TXC path
+ * to get the required clock skews.
+ */
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0070);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x7777);
+	/* tx data pad skew - devaddr = 0x02, register = 0x06 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03f4);
 
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
@@ -40,27 +115,379 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(1, 0x72);
+	} else if (port == &port2) {
+		debug("Setup pd switch on port 2\n");
+		return setup_pd_switch(1, 0x73);
+	} else
+		return -EINVAL;
+}
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x52,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	} else if (tcpc_pd_sink_check_charging(&port2)) {
+		/* Disable PD for USB1, since USB2 has priority */
+		port1_config.disable_pd = true;
+		printf("Power supply on USB2\n");
+	}
+
+	debug("tcpc_init port 1\n");
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	} else {
+		if (!port1_config.disable_pd)
+			printf("Power supply on USB1\n");
+		return ret;
+	}
+
+	return ret;
+}
+#endif /* CONFIG_USB_TCPC */
+
+#ifdef CONFIG_USB_EHCI_HCD
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+#ifdef CONFIG_USB_TCPC
+	struct tcpc_port *port_ptr;
+#endif
+
+	debug("board_usb_init %d, type %d\n", index, init);
+
+	imx8m_usb_power(index, true);
+
+#ifdef CONFIG_USB_TCPC
+	if (index == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(port_ptr);
+	else
+		tcpc_setup_ufp_mode(port_ptr);
+#endif
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	debug("board_usb_cleanup %d, type %d\n", index, init);
+
+#ifdef CONFIG_USB_TCPC
+	if (init == USB_INIT_HOST) {
+		if (index == 0)
+			ret = tcpc_disable_src_vbus(&port1);
+		else
+			ret = tcpc_disable_src_vbus(&port2);
+	}
+#endif
+
+	imx8m_usb_power(index, false);
+	return ret;
+}
+
+#ifdef CONFIG_SPL_BUILD
+int board_usb_phy_mode(struct udevice *dev)
+#else
+int board_ehci_usb_phy_mode(struct udevice *dev)
+#endif
+{
+#ifdef CONFIG_USB_TCPC
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	struct tcpc_port *port_ptr;
+
+	if (dev->seq == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	tcpc_setup_ufp_mode(port_ptr);
+
+	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+#endif /* CONFIG_USB_TCPC */
+
+	return USB_INIT_DEVICE;
+}
+#endif
+
 int board_init(void)
 {
-	if (IS_ENABLED(CONFIG_FEC_MXC))
-		setup_fec();
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
 
 	return 0;
 }
 
-int board_mmc_get_env_dev(int devno)
+#ifdef CONFIG_VIDEO_MXS
+
+/* TODO: video integration */
+#define ADV7535_MAIN 0x3d
+#define ADV7535_DSI_CEC 0x3c
+
+static const struct sec_mipi_dsim_plat_data imx8mm_mipi_dsim_plat_data = {
+	.version	= 0x1060200,
+	.max_data_lanes = 4,
+	.max_data_rate  = 1500000000ULL,
+	.reg_base = MIPI_DSI_BASE_ADDR,
+	.gpr_base = CSI_BASE_ADDR + 0x8000,
+};
+
+#define DISPLAY_MIX_SFT_RSTN_CSR		0x00
+#define DISPLAY_MIX_CLK_EN_CSR		0x04
+
+   /* 'DISP_MIX_SFT_RSTN_CSR' bit fields */
+#define BUS_RSTN_BLK_SYNC_SFT_EN	BIT(6)
+
+   /* 'DISP_MIX_CLK_EN_CSR' bit fields */
+#define LCDIF_PIXEL_CLK_SFT_EN		BIT(7)
+#define LCDIF_APB_CLK_SFT_EN		BIT(6)
+
+void disp_mix_bus_rstn_reset(ulong gpr_base, bool reset)
 {
-	return devno;
+	if (!reset)
+		/* release reset */
+		setbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN);
+	else
+		/* hold reset */
+		clrbits_le32(gpr_base + DISPLAY_MIX_SFT_RSTN_CSR, BUS_RSTN_BLK_SYNC_SFT_EN);
 }
 
+void disp_mix_lcdif_clks_enable(ulong gpr_base, bool enable)
+{
+	if (enable)
+		/* enable lcdif clks */
+		setbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
+	else
+		/* disable lcdif clks */
+		clrbits_le32(gpr_base + DISPLAY_MIX_CLK_EN_CSR, LCDIF_PIXEL_CLK_SFT_EN | LCDIF_APB_CLK_SFT_EN);
+}
+
+struct mipi_dsi_client_dev adv7535_dev = {
+	.channel	= 0,
+	.lanes = 4,
+	.format  = MIPI_DSI_FMT_RGB888,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			  MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
+	.name = "ADV7535",
+};
+
+struct mipi_dsi_client_dev rm67191_dev = {
+	.channel	= 0,
+	.lanes = 4,
+	.format  = MIPI_DSI_FMT_RGB888,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			  MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
+};
+
+#define FSL_SIP_GPC			0xC2000000
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x3
+#define DISPMIX				9
+#define MIPI				10
+
+void do_enable_mipi2hdmi(struct display_info_t const *dev)
+{
+	gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
+	gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
+
+	/* ADV7353 initialization */
+/* TODO: disable for now
+	adv7535_init(); */
+
+	/* enable the dispmix & mipi phy power domain */
+	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
+	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
+
+	/* Put lcdif out of reset */
+	disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
+	disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
+
+	/* Setup mipi dsim */
+	sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
+	imx_mipi_dsi_bridge_attach(&adv7535_dev); /* attach adv7535 device */
+}
+
+void do_enable_mipi_led(struct display_info_t const *dev)
+{
+	gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
+	gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
+	mdelay(100);
+	gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
+
+	/* enable the dispmix & mipi phy power domain */
+	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, DISPMIX, true, 0);
+	call_imx_sip(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_PM_DOMAIN, MIPI, true, 0);
+
+	/* Put lcdif out of reset */
+	disp_mix_bus_rstn_reset(imx8mm_mipi_dsim_plat_data.gpr_base, false);
+	disp_mix_lcdif_clks_enable(imx8mm_mipi_dsim_plat_data.gpr_base, true);
+
+	/* Setup mipi dsim */
+	sec_mipi_dsim_setup(&imx8mm_mipi_dsim_plat_data);
+
+	rm67191_init();
+	rm67191_dev.name = displays[1].mode.name;
+	imx_mipi_dsi_bridge_attach(&rm67191_dev); /* attach rm67191 device */
+}
+
+void board_quiesce_devices(void)
+{
+	gpio_request(IMX_GPIO_NR(1, 8), "DSI EN");
+	gpio_direction_output(IMX_GPIO_NR(1, 8), 0);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = LCDIF_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_mipi2hdmi,
+	.mode	= {
+		.name			= "MIPI2HDMI",
+		.refresh		= 60,
+		.xres			= 1920,
+		.yres			= 1080,
+		.pixclock		= 6734, /* 148500000 */
+		.left_margin	= 148,
+		.right_margin	= 88,
+		.upper_margin	= 36,
+		.lower_margin	= 4,
+		.hsync_len		= 44,
+		.vsync_len		= 5,
+		.sync			= FB_SYNC_EXT,
+		.vmode			= FB_VMODE_NONINTERLACED
+
+} }, {
+	.bus = LCDIF_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_mipi_led,
+	.mode	= {
+		.name			= "RM67191_OLED",
+		.refresh		= 60,
+		.xres			= 1080,
+		.yres			= 1920,
+		.pixclock		= 7575, /* 132000000 */
+		.left_margin	= 34,
+		.right_margin	= 20,
+		.upper_margin	= 4,
+		.lower_margin	= 10,
+		.hsync_len		= 2,
+		.vsync_len		= 2,
+		.sync			= FB_SYNC_EXT,
+		.vmode			= FB_VMODE_NONINTERLACED
+
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif /* CONFIG_VIDEO_MXS */
+
 int board_late_init(void)
 {
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
 {
-	return 0;
+	return 0; /* TODO */
 }
-#endif
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index b93ba70dcf..a36ab87e07 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -11,12 +11,13 @@ CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_ENV_OFFSET=0xFFFFDE0
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_VERDIN_IMX8MM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_DISTRO_DEFAULTS=y
@@ -25,22 +26,22 @@ CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/verdin-imx8mm/imximage.cfg"
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000"
+CONFIG_BOOTDELAY=1
 CONFIG_LOG=y
-CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-verdin-dev.dtb"
-CONFIG_VERSION_VARIABLE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-verdin.dtb"
 CONFIG_BOARD_LATE_INIT=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_PROMPT="Verdin iMX8MM # "
 # CONFIG_BOOTM_NETBSD is not set
-CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_CRC32 is not set
@@ -50,48 +51,56 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_CACHE=y
-CONFIG_CMD_UUID=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8mm-verdin"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_IP_DEFRAG=y
-CONFIG_TFTP_BLOCKSIZE=4096
-CONFIG_SPL_DM=y
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MM=y
 CONFIG_CLK_IMX8MM=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_MISC=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
-CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
 CONFIG_DM_ETH=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_DM_PMIC=y
-CONFIG_DM_PMIC_PFUZE100=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
-CONFIG_SYSRESET_PSCI=y
 CONFIG_DM_THERMAL=y
+CONFIG_NXP_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_ADV7535=y
diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h
index dc0a2efec6..cc85ff25a7 100644
--- a/include/configs/verdin-imx8mm.h
+++ b/include/configs/verdin-imx8mm.h
@@ -1,25 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2020 Toradex
+ * Copyright 2019 Toradex
  */
 
 #ifndef __VERDIN_IMX8MM_H
 #define __VERDIN_IMX8MM_H
 
-#include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
 
-#ifdef CONFIG_SECURE_BOOT
-#define CONFIG_CSF_SIZE			SZ_8K
-#endif
+#include "imx_env.h"
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 
 #define CONFIG_SPL_MAX_SIZE		(148 * 1024)
-#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
-#define CONFIG_SYS_UBOOT_BASE	\
-	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#define CONFIG_SYS_UBOOT_BASE		(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_STACK		0x920000
@@ -32,7 +31,43 @@
 #define CONFIG_MALLOC_F_ADDR		0x930000
 /* For RAW image gives a error info not panic */
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
-#endif
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_BD71837
+
+#define CONFIG_SYS_I2C
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_POSTCLK_INIT
+
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		7
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE			0x30BE0000
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP		192.168.10.1
+#endif /* CONFIG_CMD_NET */
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"fdt_addr_r=0x44000000\0" \
@@ -48,6 +83,7 @@
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 1) \
 	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #undef CONFIG_ISO_PARTITION
@@ -66,63 +102,87 @@
 	"initrd_addr=0x43800000\0" \
 	"initrd_high=0xffffffffffffffff\0" \
 	"kernel_image=Image\0" \
-	"setup=setenv setupargs console=${console},${baudrate} " \
-		"console=tty1 consoleblank=0 earlycon\0" \
-	"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
-		"if test \"$confirm\" = \"y\"; then " \
-		"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
-		"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \
-		"${blkcnt}; fi\0"
-
-#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        SZ_2M
+	"setup=setenv setupargs console=${console},${baudrate} console=tty1 consoleblank=0 earlycon\0"
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x80000
 #define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 #define CONFIG_ENV_OVERWRITE
 #if defined(CONFIG_ENV_IS_IN_MMC)
 /* Environment in eMMC, before config block at the end of 1st "boot sector" */
-#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 eMMC */
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_OFFSET
+
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_SYS_MMC_ENV_PART	1
 #endif
 
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* Increase max gunzip size */
+
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		SZ_32M
-#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32*1024)) * 1024)
 
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_2G /* 2GB DDR */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE		0x80000000 /* 2GB DDR */
 
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
-					 (PHYS_SDRAM_SIZE >> 1))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE		115200
 
-/* UART */
 #define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_CBSIZE		SZ_2K
+#define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_MAXARGS		64
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
-/* USDHC */
-#define CONFIG_FSL_USDHC
+
+#define CONFIG_IMX_BOOTAUX
+
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
-#define CONFIG_SYS_I2C_SPEED		100000
 
-/* ENET */
-#define CONFIG_ETHPRIME                 "FEC"
-#define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_FEC_MXC_PHYADDR          7
-#define FEC_QUIRK_ENET_MAC
-#define IMX_FEC_BASE			0x30BE0000
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
 
-#endif /*_VERDIN_IMX8MM_H */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#endif
+#define CONFIG_SYS_I2C_SPEED		100000
 
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+/* TODO moving USB_STORAGE to .config makes the SPL build fail */
+//#define CONFIG_USB_STORAGE
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#endif /* !CONFIG_SPL_BUILD */
+
+#define CONFIG_MXC_USB_PORTSC			(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_RM67191
+#endif /* CONFIG_VIDEO */
+
+#endif /* __VERDIN_IMX8MM_H */