diff options
| author | Ranjith Lohithakshan <ranjithl@ti.com> | 2009-09-24 15:46:54 +0530 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-21 16:46:36 -0400 |
| commit | 501ba8d5ca49922667d72c231edf8ec76e21a3da (patch) | |
| tree | 3b65708da7e728e43761f9188f813fb730c702ee | |
| parent | 5bacf4a128c044b085e7705433cfbe984f6cfae8 (diff) | |
OMAP3517: Update DDR Phy Control1 register configuration
Clear STRBEN_EXT, PWRDN_DIS and VTP_DYN bits.
Signed-off-by: Ranjith Lohithakshan <ranjithl@ti.com>
| -rw-r--r-- | cpu/arm_cortexa8/omap3/mem.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 41417326f6..2aecd74ec9 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -81,10 +81,10 @@ * EMIF4 PHY Control 1 register configuration */ #define EMIF4_DDR1_READ_LAT 0x6 -#define EMIF4_DDR1_PWRDN_DIS 0x1 -#define EMIF4_DDR1_STRBEN_EXT 0x1 +#define EMIF4_DDR1_PWRDN_DIS 0x0 +#define EMIF4_DDR1_STRBEN_EXT 0x0 #define EMIF4_DDR1_DLL_MODE 0x0 -#define EMIF4_DDR1_VTP_DYN 0x1 +#define EMIF4_DDR1_VTP_DYN 0x0 #define EMIF4_DDR1_LB_CK_SEL 0x0 #endif @@ -284,7 +284,7 @@ void emif4_init(void) { unsigned int regval; /* Set the DDR PHY parameters in PHY ctrl registers */ - regval = (EMIF4_DDR1_READ_LAT | (EMIF4_DDR1_VTP_DYN << 15) | + regval = (EMIF4_DDR1_READ_LAT | (EMIF4_DDR1_PWRDN_DIS << 6) | (EMIF4_DDR1_STRBEN_EXT << 7) | (EMIF4_DDR1_DLL_MODE << 12) | (EMIF4_DDR1_VTP_DYN << 15) | (EMIF4_DDR1_LB_CK_SEL << 23)); writel(regval, &emif4_base->ddr_phyctrl1); |