summaryrefslogtreecommitdiff
path: root/drivers/clk/imx/clk-mux-scu.c
blob: ac1c8bc385bd18bd5e3d39c65d9b01b64375217f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <soc/imx8/sc/sci.h>

#include "clk-imx8.h"

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */

struct clk_mux_scu {
	struct clk_hw	hw;
	void __iomem	*reg;
	u32		*table;
	u32		mask;
	u8		shift;
	u8		flags;
	u32		val;
	bool		update;
	spinlock_t	*lock;
	char *pd_name;
	struct generic_pm_domain *pd;
};

struct clk_mux_gpr_scu {
	struct clk_hw hw;
	sc_rsrc_t	rsrc_id;
	sc_ctrl_t	gpr_id;
};

struct clk_mux2_scu {
	struct clk_hw	hw;
	sc_rsrc_t	rsrc_id;
	sc_pm_clk_t	clk_type;
};

#define to_clk_mux_scu(_hw) container_of(_hw, struct clk_mux_scu, hw)
#define to_clk_mux_gpr_scu(_hw) container_of(_hw, struct clk_mux_gpr_scu, hw)
#define to_clk_mux2_scu(_hw) container_of(_hw, struct clk_mux2_scu, hw)

/* Get the power domain associated with the clock from the device tree. */
static void populate_mux_pd(struct clk_mux_scu *clk)
{
	struct device_node *np;
	struct of_phandle_args pd_args;

	np = of_find_node_by_name(NULL, clk->pd_name);
	if (np) {
		pd_args.np = np;
		pd_args.args_count = 0;
		clk->pd = genpd_get_from_provider(&pd_args);
		if (IS_ERR(clk->pd))
			pr_warn("%s: failed to get pd\n", __func__);
	}
}

static int check_mux_pd(struct clk_mux_scu *mux)
{
	if (!ccm_ipc_handle)
		return -1;

	if (mux->pd == NULL && mux->pd_name)
		populate_mux_pd(mux);

	if (IS_ERR_OR_NULL(mux->pd))
		return -1;

	if (mux->pd->status != GPD_STATE_ACTIVE)
		return -1;

	return 0;
}

static u8 clk_mux_get_parent_scu(struct clk_hw *hw)
{
	struct clk_mux_scu *mux = to_clk_mux_scu(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 val;

	/*
	 * FIXME need a mux-specific flag to determine if val is bitwise or numeric
	 * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
	 * to 0x7 (index starts at one)
	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
	 * val = 0x4 really means "bit 2, index starts at bit 0"
	 */
	val = mux->val >> mux->shift;
	val &= mux->mask;

	if (mux->table) {
		int i;

		for (i = 0; i < num_parents; i++)
			if (mux->table[i] == val)
				return i;
		return -EINVAL;
	}

	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
		val = ffs(val) - 1;

	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
		val--;

	if (val >= num_parents)
		return -EINVAL;

	return val;
}

static int clk_mux_prepare_scu(struct clk_hw *hw)
{
	struct clk_mux_scu *mux = to_clk_mux_scu(hw);
	unsigned long flags = 0;
	int ret;

	ret = check_mux_pd(mux);
	if (ret)
		return ret;

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);

	if (mux->update) {
		clk_writel(mux->val, mux->reg);
		mux->update = 0;
	}

	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);

	return 0;
}

static int clk_mux_set_parent_scu(struct clk_hw *hw, u8 index)
{
	struct clk_mux_scu *mux = to_clk_mux_scu(hw);
	unsigned long flags = 0;
	int ret;

	ret = check_mux_pd(mux);

	if (mux->table) {
		index = mux->table[index];
	} else {
		if (mux->flags & CLK_MUX_INDEX_BIT)
			index = 1 << index;
		if (mux->flags & CLK_MUX_INDEX_ONE)
			index++;
	}

	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);

	if (mux->flags & CLK_MUX_HIWORD_MASK) {
		mux->val = mux->mask << (mux->shift + 16);
	} else {
		mux->val &= ~(mux->mask << mux->shift);
	}
	mux->val |= index << mux->shift;
	mux->update = (ret != 0);

	if (ret == 0)
		clk_writel(mux->val, mux->reg);

	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);

	return 0;
}

const struct clk_ops clk_mux_scu_ops = {
	.prepare = clk_mux_prepare_scu,
	.get_parent = clk_mux_get_parent_scu,
	.set_parent = clk_mux_set_parent_scu,
	.determine_rate = __clk_mux_determine_rate,
};

const struct clk_ops clk_mux_ro_scu_ops = {
	.get_parent = clk_mux_get_parent_scu,
};

struct clk *clk_register_mux_table_scu(struct device *dev, const char *name,
		const char **parent_names, u8 num_parents, unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock,
		const char *pd_name)
{
	struct clk_mux_scu *mux;
	struct clk *clk;
	struct clk_init_data init;
	u8 width = 0;

	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
		width = fls(mask) - ffs(mask) + 1;
		if (width + shift > 16) {
			pr_err("mux value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}

	/* allocate the mux */
	mux = kzalloc(sizeof(struct clk_mux_scu), GFP_KERNEL);
	if (!mux) {
		pr_err("%s: could not allocate mux clk\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	init.name = name;
	if (clk_mux_flags & CLK_MUX_READ_ONLY)
		init.ops = &clk_mux_ro_scu_ops;
	else
		init.ops = &clk_mux_scu_ops;
	init.flags = flags | CLK_IS_BASIC;
	init.parent_names = parent_names;
	init.num_parents = num_parents;

	/* struct clk_mux_scu assignments */
	mux->reg = reg;
	mux->shift = shift;
	mux->mask = mask;
	mux->flags = clk_mux_flags;
	mux->lock = lock;
	mux->table = table;
	mux->hw.init = &init;
	mux->pd_name = NULL;
	if (pd_name) {
		mux->pd_name = kzalloc(strlen(pd_name) + 1, GFP_KERNEL);
		strcpy(mux->pd_name, pd_name);
	}

	clk = clk_register(dev, &mux->hw);

	if (IS_ERR(clk)) {
		kfree(mux->pd_name);
		kfree(mux);
	}

	return clk;
}

struct clk *clk_register_mux_scu(struct device *dev, const char *name,
		const char **parent_names, u8 num_parents, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock,
		const char *pd_name)
{
	u32 mask = BIT(width) - 1;

	return clk_register_mux_table_scu(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock, pd_name);
}

void clk_unregister_mux_scu(struct clk *clk)
{
	struct clk_mux_scu *mux;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	mux = to_clk_mux_scu(hw);

	clk_unregister(clk);
	kfree(mux);
}

static u8 clk_mux_gpr_scu_get_parent(struct clk_hw *hw)
{
	struct clk_mux_gpr_scu *gpr_mux = to_clk_mux_gpr_scu(hw);
	u32 val = 0;

	if (!ccm_ipc_handle)
		return 0;

	sc_misc_get_control(ccm_ipc_handle,
		gpr_mux->rsrc_id, gpr_mux->gpr_id, &val);

	return (u8)val;
}

static int clk_mux_gpr_scu_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux_gpr_scu *gpr_mux = to_clk_mux_gpr_scu(hw);

	if (!ccm_ipc_handle)
		return -1;

	sc_misc_set_control(ccm_ipc_handle,
		gpr_mux->rsrc_id, gpr_mux->gpr_id, index);

	return 0;
}

static const struct clk_ops clk_mux_gpr_scu_ops = {
	.get_parent = clk_mux_gpr_scu_get_parent,
	.set_parent = clk_mux_gpr_scu_set_parent,
};

struct clk *clk_register_mux_gpr_scu(struct device *dev, const char *name,
		const char **parents, int num_parents, spinlock_t *lock,
		sc_rsrc_t rsrc_id, sc_ctrl_t gpr_id)
{
	struct clk_mux_gpr_scu *gpr_scu_mux;
	struct clk *clk;
	struct clk_init_data init;

	if (!imx8_clk_is_resource_owned(rsrc_id)) {
		pr_debug("skip clk %s rsrc %d not owned\n", name, rsrc_id);
		return ERR_PTR(-ENODEV);
	}

	if (rsrc_id >= SC_R_LAST)
		return NULL;

	if (gpr_id >= SC_C_LAST)
		return NULL;

	gpr_scu_mux = kzalloc(sizeof(struct clk_mux_gpr_scu), GFP_KERNEL);
	if (!gpr_scu_mux)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &clk_mux_gpr_scu_ops;
	init.parent_names = parents;
	init.num_parents = num_parents;
	init.flags |= CLK_SET_PARENT_NOCACHE;

	gpr_scu_mux->hw.init = &init;
	gpr_scu_mux->rsrc_id = rsrc_id;
	gpr_scu_mux->gpr_id = gpr_id;

	clk = clk_register(NULL, &gpr_scu_mux->hw);
	if (IS_ERR(clk))
		kfree(gpr_scu_mux);

	return clk;
}

static u8 clk_mux2_scu_get_parent(struct clk_hw *hw)
{
	struct clk_mux2_scu *mux = to_clk_mux2_scu(hw);
	sc_pm_clk_parent_t parent;
	sc_err_t ret;

	if (!ccm_ipc_handle)
		return -EBUSY;

	ret = sc_pm_get_clock_parent(ccm_ipc_handle, mux->rsrc_id,
				     mux->clk_type, &parent);
	if (ret != SC_ERR_NONE)
		return -EINVAL;

	return (u8)parent;
}

static int clk_mux2_scu_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux2_scu *mux = to_clk_mux2_scu(hw);
	sc_err_t ret;

	if (!ccm_ipc_handle)
		return -EBUSY;

	ret = sc_pm_set_clock_parent(ccm_ipc_handle, mux->rsrc_id,
				     mux->clk_type, index);
	if (ret != SC_ERR_NONE)
		return -EINVAL;

	return 0;
}

static const struct clk_ops clk_mux2_scu_ops = {
	.get_parent = clk_mux2_scu_get_parent,
	.set_parent = clk_mux2_scu_set_parent,
};


struct clk *clk_register_mux2_scu(struct device *dev, const char *name,
				  const char **parents, int num_parents,
				  unsigned long flags, sc_rsrc_t rsrc_id,
				  sc_pm_clk_t clk_type)
{
	struct clk_mux2_scu *mux;
	struct clk *clk;
	struct clk_init_data init;

	if (!imx8_clk_is_resource_owned(rsrc_id)) {
		pr_debug("skip clk %s rsrc %d not owned\n", name, rsrc_id);
		return ERR_PTR(-ENODEV);
	}

	if (rsrc_id >= SC_R_LAST)
		return ERR_PTR(-EINVAL);

	mux = kzalloc(sizeof(struct clk_mux2_scu), GFP_KERNEL);
	if (!mux)
		return ERR_PTR(-ENOMEM);

	init.name = name;
	init.ops = &clk_mux2_scu_ops;
	init.parent_names = parents;
	init.num_parents = num_parents;
	init.flags = flags |= CLK_SET_PARENT_NOCACHE;

	mux->hw.init = &init;
	mux->rsrc_id = rsrc_id;
	mux->clk_type = clk_type;

	clk = clk_register(NULL, &mux->hw);
	if (IS_ERR(clk))
		kfree(mux);

	return clk;
}