1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8mq-evk.dts"
&hdmi {
status = "disabled";
};
&dcss {
status = "okay";
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <600000000>,
<800000000>,
<400000000>,
<0>,
<400000000>,
<599999999>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_dsi_phy {
status = "okay";
};
&mipi_dsi {
status = "okay";
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
<&clk IMX8MQ_CLK_DSI_CORE_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <24000000>,
<266000000>,
<0>,
<599999999>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&dcss_disp0_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "okay";
panel@0 {
compatible = "raydium,rm67191";
reg = <0>;
pinctrl-0 = <&pinctrl_mipi_dsi_en>;
reset-gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
dsi-lanes = <4>;
panel-width-mm = <68>;
panel-height-mm = <121>;
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@1 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&iomuxc {
imx8mq-evk {
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
pinctrl_i2c1_synaptics_dsx_io: synaptics_dsx_iogrp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19
>;
};
};
};
&i2c1 {
synaptics_dsx_ts@20 {
compatible = "synaptics_dsx";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_synaptics_dsx_io>;
interrupt-parent = <&gpio5>;
interrupts = <7 8>;
synaptics,diagonal-rotation;
status = "okay";
};
};
|
