blob: 54cee651949668b508f28153e7e002397d43250d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
|
/*
* STMP SPDIF Register Definitions
*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This file is created by xml file. Don't Edit it.
*/
#ifndef __ARCH_ARM___SPDIF_H
#define __ARCH_ARM___SPDIF_H 1
#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
#define REGS_SPDIF_PHYS (0x80054000)
#define REGS_SPDIF_SIZE 0x00002000
#define HW_SPDIF_CTRL (0x00000000)
#define HW_SPDIF_CTRL_SET (0x00000004)
#define HW_SPDIF_CTRL_CLR (0x00000008)
#define HW_SPDIF_CTRL_TOG (0x0000000c)
#define HW_SPDIF_CTRL_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_CTRL)
#define HW_SPDIF_CTRL_SET_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET)
#define HW_SPDIF_CTRL_CLR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR)
#define HW_SPDIF_CTRL_TOG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_CTRL_TOG)
#define BM_SPDIF_CTRL_SFTRST 0x80000000
#define BM_SPDIF_CTRL_CLKGATE 0x40000000
#define BP_SPDIF_CTRL_RSRVD1 21
#define BM_SPDIF_CTRL_RSRVD1 0x3FE00000
#define BF_SPDIF_CTRL_RSRVD1(v) \
(((v) << 21) & BM_SPDIF_CTRL_RSRVD1)
#define BP_SPDIF_CTRL_DMAWAIT_COUNT 16
#define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x001F0000
#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) \
(((v) << 16) & BM_SPDIF_CTRL_DMAWAIT_COUNT)
#define BP_SPDIF_CTRL_RSRVD0 6
#define BM_SPDIF_CTRL_RSRVD0 0x0000FFC0
#define BF_SPDIF_CTRL_RSRVD0(v) \
(((v) << 6) & BM_SPDIF_CTRL_RSRVD0)
#define BM_SPDIF_CTRL_WAIT_END_XFER 0x00000020
#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
#define BM_SPDIF_CTRL_RUN 0x00000001
#define HW_SPDIF_STAT (0x00000010)
#define HW_SPDIF_STAT_SET (0x00000014)
#define HW_SPDIF_STAT_CLR (0x00000018)
#define HW_SPDIF_STAT_TOG (0x0000001c)
#define HW_SPDIF_STAT_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_STAT)
#define HW_SPDIF_STAT_SET_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_STAT_SET)
#define HW_SPDIF_STAT_CLR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_STAT_CLR)
#define HW_SPDIF_STAT_TOG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_STAT_TOG)
#define BM_SPDIF_STAT_PRESENT 0x80000000
#define BP_SPDIF_STAT_RSRVD1 1
#define BM_SPDIF_STAT_RSRVD1 0x7FFFFFFE
#define BF_SPDIF_STAT_RSRVD1(v) \
(((v) << 1) & BM_SPDIF_STAT_RSRVD1)
#define BM_SPDIF_STAT_END_XFER 0x00000001
#define HW_SPDIF_FRAMECTRL (0x00000020)
#define HW_SPDIF_FRAMECTRL_SET (0x00000024)
#define HW_SPDIF_FRAMECTRL_CLR (0x00000028)
#define HW_SPDIF_FRAMECTRL_TOG (0x0000002c)
#define HW_SPDIF_FRAMECTRL_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL)
#define HW_SPDIF_FRAMECTRL_SET_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_SET)
#define HW_SPDIF_FRAMECTRL_CLR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_CLR)
#define HW_SPDIF_FRAMECTRL_TOG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_TOG)
#define BP_SPDIF_FRAMECTRL_RSRVD2 18
#define BM_SPDIF_FRAMECTRL_RSRVD2 0xFFFC0000
#define BF_SPDIF_FRAMECTRL_RSRVD2(v) \
(((v) << 18) & BM_SPDIF_FRAMECTRL_RSRVD2)
#define BM_SPDIF_FRAMECTRL_V_CONFIG 0x00020000
#define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x00010000
#define BM_SPDIF_FRAMECTRL_RSRVD1 0x00008000
#define BM_SPDIF_FRAMECTRL_USER_DATA 0x00004000
#define BM_SPDIF_FRAMECTRL_V 0x00002000
#define BM_SPDIF_FRAMECTRL_L 0x00001000
#define BM_SPDIF_FRAMECTRL_RSRVD0 0x00000800
#define BP_SPDIF_FRAMECTRL_CC 4
#define BM_SPDIF_FRAMECTRL_CC 0x000007F0
#define BF_SPDIF_FRAMECTRL_CC(v) \
(((v) << 4) & BM_SPDIF_FRAMECTRL_CC)
#define BM_SPDIF_FRAMECTRL_PRE 0x00000008
#define BM_SPDIF_FRAMECTRL_COPY 0x00000004
#define BM_SPDIF_FRAMECTRL_AUDIO 0x00000002
#define BM_SPDIF_FRAMECTRL_PRO 0x00000001
#define HW_SPDIF_SRR (0x00000030)
#define HW_SPDIF_SRR_SET (0x00000034)
#define HW_SPDIF_SRR_CLR (0x00000038)
#define HW_SPDIF_SRR_TOG (0x0000003c)
#define HW_SPDIF_SRR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_SRR)
#define HW_SPDIF_SRR_SET_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_SRR_SET)
#define HW_SPDIF_SRR_CLR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_SRR_CLR)
#define HW_SPDIF_SRR_TOG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_SRR_TOG)
#define BM_SPDIF_SRR_RSRVD1 0x80000000
#define BP_SPDIF_SRR_BASEMULT 28
#define BM_SPDIF_SRR_BASEMULT 0x70000000
#define BF_SPDIF_SRR_BASEMULT(v) \
(((v) << 28) & BM_SPDIF_SRR_BASEMULT)
#define BP_SPDIF_SRR_RSRVD0 20
#define BM_SPDIF_SRR_RSRVD0 0x0FF00000
#define BF_SPDIF_SRR_RSRVD0(v) \
(((v) << 20) & BM_SPDIF_SRR_RSRVD0)
#define BP_SPDIF_SRR_RATE 0
#define BM_SPDIF_SRR_RATE 0x000FFFFF
#define BF_SPDIF_SRR_RATE(v) \
(((v) << 0) & BM_SPDIF_SRR_RATE)
#define HW_SPDIF_DEBUG (0x00000040)
#define HW_SPDIF_DEBUG_SET (0x00000044)
#define HW_SPDIF_DEBUG_CLR (0x00000048)
#define HW_SPDIF_DEBUG_TOG (0x0000004c)
#define HW_SPDIF_DEBUG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DEBUG)
#define HW_SPDIF_DEBUG_SET_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DEBUG_SET)
#define HW_SPDIF_DEBUG_CLR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DEBUG_CLR)
#define HW_SPDIF_DEBUG_TOG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DEBUG_TOG)
#define BP_SPDIF_DEBUG_RSRVD1 2
#define BM_SPDIF_DEBUG_RSRVD1 0xFFFFFFFC
#define BF_SPDIF_DEBUG_RSRVD1(v) \
(((v) << 2) & BM_SPDIF_DEBUG_RSRVD1)
#define BM_SPDIF_DEBUG_DMA_PREQ 0x00000002
#define BM_SPDIF_DEBUG_FIFO_STATUS 0x00000001
#define HW_SPDIF_DATA (0x00000050)
#define HW_SPDIF_DATA_SET (0x00000054)
#define HW_SPDIF_DATA_CLR (0x00000058)
#define HW_SPDIF_DATA_TOG (0x0000005c)
#define HW_SPDIF_DATA_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DATA)
#define HW_SPDIF_DATA_SET_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DATA_SET)
#define HW_SPDIF_DATA_CLR_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DATA_CLR)
#define HW_SPDIF_DATA_TOG_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_DATA_TOG)
#define BP_SPDIF_DATA_HIGH 16
#define BM_SPDIF_DATA_HIGH 0xFFFF0000
#define BF_SPDIF_DATA_HIGH(v) \
(((v) << 16) & BM_SPDIF_DATA_HIGH)
#define BP_SPDIF_DATA_LOW 0
#define BM_SPDIF_DATA_LOW 0x0000FFFF
#define BF_SPDIF_DATA_LOW(v) \
(((v) << 0) & BM_SPDIF_DATA_LOW)
#define HW_SPDIF_VERSION (0x00000060)
#define HW_SPDIF_VERSION_ADDR \
(REGS_SPDIF_BASE + HW_SPDIF_VERSION)
#define BP_SPDIF_VERSION_MAJOR 24
#define BM_SPDIF_VERSION_MAJOR 0xFF000000
#define BF_SPDIF_VERSION_MAJOR(v) \
(((v) << 24) & BM_SPDIF_VERSION_MAJOR)
#define BP_SPDIF_VERSION_MINOR 16
#define BM_SPDIF_VERSION_MINOR 0x00FF0000
#define BF_SPDIF_VERSION_MINOR(v) \
(((v) << 16) & BM_SPDIF_VERSION_MINOR)
#define BP_SPDIF_VERSION_STEP 0
#define BM_SPDIF_VERSION_STEP 0x0000FFFF
#define BF_SPDIF_VERSION_STEP(v) \
(((v) << 0) & BM_SPDIF_VERSION_STEP)
#endif /* __ARCH_ARM___SPDIF_H */
|
