From 746183c0038fa0338ad2ac3fb3ec1b9ebe909af8 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Wed, 27 Aug 2014 16:31:13 -0700 Subject: media: tegra_v4l2_camera: set clock rate for pll_d Test pattern generator in VI needs PLL_D running at certain clock rate, then CSI clock is a child of PLL_D can get the right clock for operation. If DC disable DSI and set PLL_D as a very low frequency and VI driver forgets to set PLL_D rate back, test pattern generator won't work. This patch will set PLL_D as 927M when we do test pattern generator testing. Bug 1515755 Change-Id: I8fd27d193a436e1057ce2bce8f8153630dc5cdce Signed-off-by: Bryan Wu Reviewed-on: http://git-master/r/489043 (cherry picked from commit e09393ad2a02309f63a3baeb567460e1e2f79cd9) Reviewed-on: http://git-master/r/498938 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro Reviewed-by: Winnie Hsu --- drivers/media/platform/soc_camera/tegra_camera/vi2.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'drivers/media/platform/soc_camera/tegra_camera/vi2.c') diff --git a/drivers/media/platform/soc_camera/tegra_camera/vi2.c b/drivers/media/platform/soc_camera/tegra_camera/vi2.c index 95f88bfd4129..0edaac05ccdf 100644 --- a/drivers/media/platform/soc_camera/tegra_camera/vi2.c +++ b/drivers/media/platform/soc_camera/tegra_camera/vi2.c @@ -273,7 +273,7 @@ static struct tegra_camera_clk vi2_clks0[] = { /* Always put "p11_d" at the end */ { .name = "pll_d", - .freq = 0, + .freq = 927000000, }, }; @@ -317,7 +317,7 @@ static struct tegra_camera_clk vi2_clks1[] = { /* Always put "p11_d" at the end */ { .name = "pll_d", - .freq = 0, + .freq = 927000000, }, }; @@ -358,9 +358,6 @@ static int vi2_clks_init(struct tegra_camera_dev *cam) clks->name); return PTR_ERR(clks->clk); } - - if (clks->freq > 0) - clk_set_rate(clks->clk, clks->freq); } return 0; @@ -387,12 +384,16 @@ static void vi2_clks_enable(struct tegra_camera_dev *cam) clks = &cam->clks[i]; if (clks->clk) clk_prepare_enable(clks->clk); + if (clks->freq > 0) + clk_set_rate(clks->clk, clks->freq); } if (cam->tpg_mode) { clks = &cam->clks[i]; if (clks->clk) { clk_prepare_enable(clks->clk); + if (clks->freq > 0) + clk_set_rate(clks->clk, clks->freq); tegra_clk_cfg_ex(clks->clk, TEGRA_CLK_PLLD_CSI_OUT_ENB, 1); tegra_clk_cfg_ex(clks->clk, -- cgit v1.2.3