From c4e7ffe25d82af411c5e9cfc24e531c220fabfae Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Tue, 21 Nov 2017 13:56:50 +0800 Subject: MLK-16896 tty: serial: lpuart: flush transmit/receive fifo/buffer Although .startup() alreadly do transmit/receive fifo/buffer flush, but switch the baud rate may introduce dirty data on fifo, in such case, user will call tcflush() to clean up buffer and fifo. So driver also ensure HW fifo is cleaned up. The patch add hw fifo/buffer flush in .flush_buffer() callback. Signed-off-by: Fugang Duan --- drivers/tty/serial/fsl_lpuart.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 68200cad1266..3971bc0b0231 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -480,6 +480,8 @@ static int lpuart_dma_tx_request(struct uart_port *port) static void lpuart_flush_buffer(struct uart_port *port) { struct lpuart_port *sport = container_of(port, struct lpuart_port, port); + u32 val; + if (sport->lpuart_dma_tx_use) { if (sport->dma_tx_in_progress) { dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], @@ -488,6 +490,16 @@ static void lpuart_flush_buffer(struct uart_port *port) } dmaengine_terminate_all(sport->dma_tx_chan); } + + if (sport->lpuart32) { + val = lpuart32_read(sport->port.membase + UARTFIFO); + val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; + lpuart32_write(val, sport->port.membase + UARTFIFO); + } else { + val = readb(sport->port.membase + UARTPFIFO); + val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; + writeb(val, sport->port.membase + UARTCFIFO); + } } static inline void lpuart_transmit_buffer(struct lpuart_port *sport) -- cgit v1.2.3