From 946371b8332ba5897e5af36eb3cee2d3e7e3524e Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 27 Mar 2023 15:03:37 +0200 Subject: Revert "clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP" This reverts commit f57690a9374745357c290b56e6007a7820f11461. This series broke our 10" capacitive LVDS panel. Revert until fixed. Upstream-Status: Inappropriate [revert of backport] Signed-off-by: Max Krummenacher --- drivers/clk/imx/clk-pll14xx.c | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 298aeb1ed07b..e952b9034afc 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -3,7 +3,6 @@ * Copyright 2017-2018 NXP. */ -#include #include #include #include @@ -23,9 +22,13 @@ #define CLKE_MASK BIT(11) #define RST_MASK BIT(9) #define BYPASS_MASK BIT(4) +#define MDIV_SHIFT 12 #define MDIV_MASK GENMASK(21, 12) +#define PDIV_SHIFT 4 #define PDIV_MASK GENMASK(9, 4) +#define SDIV_SHIFT 0 #define SDIV_MASK GENMASK(2, 0) +#define KDIV_SHIFT 0 #define KDIV_MASK GENMASK(15, 0) #define LOCK_TIMEOUT_US 10000 @@ -121,9 +124,9 @@ static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw, u64 fvco = parent_rate; pll_div = readl_relaxed(pll->base + DIV_CTL0); - mdiv = FIELD_GET(MDIV_MASK, pll_div); - pdiv = FIELD_GET(PDIV_MASK, pll_div); - sdiv = FIELD_GET(SDIV_MASK, pll_div); + mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; fvco *= mdiv; do_div(fvco, pdiv << sdiv); @@ -144,10 +147,10 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw, pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1); - mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); - pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0); - sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0); - kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1); + mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; + pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; + sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; + kdiv = pll_div_ctl1 & KDIV_MASK; /* * Sometimes, the recalculated rate has deviation due to @@ -175,8 +178,8 @@ static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *ra { u32 old_mdiv, old_pdiv; - old_mdiv = FIELD_GET(MDIV_MASK, pll_div); - old_pdiv = FIELD_GET(PDIV_MASK, pll_div); + old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; + old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; } @@ -208,7 +211,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); + tmp |= rate->sdiv << SDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL0); return 0; @@ -227,8 +230,8 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel(tmp, pll->base + GNRL_CTL); - div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | + (rate->sdiv << SDIV_SHIFT); writel_relaxed(div_val, pll->base + DIV_CTL0); /* @@ -274,10 +277,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, if (!clk_pll14xx_mp_change(rate, tmp)) { tmp &= ~SDIV_MASK; - tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); + tmp |= rate->sdiv << SDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL0); - tmp = FIELD_PREP(KDIV_MASK, rate->kdiv); + tmp = rate->kdiv << KDIV_SHIFT; writel_relaxed(tmp, pll->base + DIV_CTL1); return 0; @@ -292,11 +295,10 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, tmp |= BYPASS_MASK; writel_relaxed(tmp, pll->base + GNRL_CTL); - div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | - FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); + div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | + (rate->sdiv << SDIV_SHIFT); writel_relaxed(div_val, pll->base + DIV_CTL0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); + writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + DIV_CTL1); /* * According to SPEC, t3 - t2 need to be greater than -- cgit v1.2.3