From 72928ca0214c76e4d7abadd6768295509a159bfa Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 19 Mar 2018 10:53:42 +0100 Subject: Revert "MLK-14498-2 ARM: imx7d: clk: select uart clock parent and rate" This seems to limit possible baud rates due to lower input clock. Since Toradex modules do not use UART5/6 as console, do not set clock explicitly. This reverts commit 4f447cb8bccb1d40973e46478d7b11aa61961c90. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- drivers/clk/imx/clk-imx7d.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index eceb055b30cf..4741ca136f98 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -940,11 +940,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) /* set parent of SIM1 root clock */ imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000); - imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART6_ROOT_DIV], 80000000); - imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); -- cgit v1.2.3