From 4742c51f570ed863b4fa57b94acfb51c2ab49cff Mon Sep 17 00:00:00 2001 From: Fugang Duan Date: Wed, 10 Dec 2014 18:55:04 +0800 Subject: MLK-10199 ARM: clk-imx6q: set enet pll rate to 125Mhz Set enet pll rate to 125Mhz for RGMII tx refrence clock to support i.MX6q sabreauto cpu2 board. Signed-off-by: Fugang Duan --- arch/arm/mach-imx/clk-imx6q.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 59cda8b89135..7ddf1cc90799 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -752,6 +752,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */ imx_clk_set_rate(clk[pll4_audio_div], 541900800); + /*Set enet_ref clock to 125M to supply for RGMII tx_clk */ + clk_set_rate(clk[enet_ref], 125000000); + #ifdef CONFIG_MX6_VPU_352M /* * If VPU 352M is enabled, then PLL2_PDF2 need to be -- cgit v1.2.3