From 360b187f21ae5f552f56b6d5e26defe83eabdccc Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 27 Mar 2023 15:02:46 +0200 Subject: Revert "clk: imx: pll14xx: name variables after usage" This reverts commit e435f17a00caf52cc3f0154367308888c4e7d676. This series broke our 10" capacitive LVDS panel. Revert until fixed. Upstream-Status: Inappropriate [revert of backport] Signed-off-by: Max Krummenacher --- drivers/clk/imx/clk-pll14xx.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index f95cb1269562..b633b0b7d8e7 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -238,7 +238,7 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, { struct clk_pll14xx *pll = to_clk_pll14xx(hw); const struct imx_pll14xx_rate_table *rate; - u32 gnrl_ctl, div_ctl0; + u32 tmp, div_val; int ret; rate = imx_get_pll_settings(pll, drate); @@ -248,32 +248,32 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return -EINVAL; } - div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + tmp = readl_relaxed(pll->base + DIV_CTL0); - if (!clk_pll14xx_mp_change(rate, div_ctl0)) { - div_ctl0 &= ~SDIV_MASK; - div_ctl0 |= FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + if (!clk_pll14xx_mp_change(rate, tmp)) { + tmp &= ~SDIV_MASK; + tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv); + writel_relaxed(tmp, pll->base + DIV_CTL0); - writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), - pll->base + DIV_CTL1); + tmp = FIELD_PREP(KDIV_MASK, rate->kdiv); + writel_relaxed(tmp, pll->base + DIV_CTL1); return 0; } /* Enable RST */ - gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL); - gnrl_ctl &= ~RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + tmp = readl_relaxed(pll->base + GNRL_CTL); + tmp &= ~RST_MASK; + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Enable BYPASS */ - gnrl_ctl |= BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + tmp |= BYPASS_MASK; + writel_relaxed(tmp, pll->base + GNRL_CTL); - div_ctl0 = FIELD_PREP(MDIV_MASK, rate->mdiv) | - FIELD_PREP(PDIV_MASK, rate->pdiv) | - FIELD_PREP(SDIV_MASK, rate->sdiv); - writel_relaxed(div_ctl0, pll->base + DIV_CTL0); + div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | + FIELD_PREP(PDIV_MASK, rate->pdiv) | + FIELD_PREP(SDIV_MASK, rate->sdiv); + writel_relaxed(div_val, pll->base + DIV_CTL0); writel_relaxed(FIELD_PREP(KDIV_MASK, rate->kdiv), pll->base + DIV_CTL1); /* @@ -285,8 +285,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, udelay(3); /* Disable RST */ - gnrl_ctl |= RST_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + tmp |= RST_MASK; + writel_relaxed(tmp, pll->base + GNRL_CTL); /* Wait Lock*/ ret = clk_pll14xx_wait_lock(pll); @@ -294,8 +294,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return ret; /* Bypass */ - gnrl_ctl &= ~BYPASS_MASK; - writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + tmp &= ~BYPASS_MASK; + writel_relaxed(tmp, pll->base + GNRL_CTL); return 0; } -- cgit v1.2.3