From 1815d04bb84d27fb239e4fad85df6cbf63a03ba9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 21 Jun 2013 11:50:01 +0200 Subject: apalis_t30: fix PCIe by forcing GEN1 speed Enable PCI quirk support resp. don't explicitly disable it in order for the following fix to take effect. The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1). The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2 PCIe Capability Register of the PEX8605 PCIe switch. The switch supports link speed auto negotiation, but falsely sets the link speed to 5 GT/s. --- arch/arm/configs/apalis_t30_defconfig | 1 - arch/arm/mach-tegra/board-apalis_t30.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/apalis_t30_defconfig b/arch/arm/configs/apalis_t30_defconfig index 18e234b4e15f..3e872b1f86d4 100644 --- a/arch/arm/configs/apalis_t30_defconfig +++ b/arch/arm/configs/apalis_t30_defconfig @@ -21,7 +21,6 @@ CONFIG_KALLSYMS_ALL=y # CONFIG_ELF_CORE is not set CONFIG_EMBEDDED=y # CONFIG_PERF_EVENTS is not set -# CONFIG_PCI_QUIRKS is not set CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=y diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c index 7af2c8f9e90b..493510bda657 100644 --- a/arch/arm/mach-tegra/board-apalis_t30.c +++ b/arch/arm/mach-tegra/board-apalis_t30.c @@ -453,6 +453,17 @@ static void __init apalis_t30_sdhci_init(void) /* PCIe */ +/* The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1). + The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2 + PCIe Capability Register of the PEX8605 PCIe switch. The switch supports + link speed auto negotiation, but falsely sets the link speed to 5 GT/s. */ +static void __devinit quirk_apalis_plx_gen1(struct pci_dev *dev) +{ + pci_write_config_dword(dev, 0x98, 0x01); + mdelay(50); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1); + static struct tegra_pci_platform_data apalis_t30_pci_platform_data = { .port_status[0] = 1, .port_status[1] = 1, -- cgit v1.2.3