From 0816d2c71400aea90e73fba260108a4eb3870dd5 Mon Sep 17 00:00:00 2001 From: Zhang Jiejing Date: Thu, 15 Mar 2012 17:09:40 +0800 Subject: ENGR00176974 MX6Q: make 624M WP work, change 624 WP to 672 WP since pll1 have a limit that cannot scaling down to 650M and below so change the 600M WP to 672MHz. otherwise, the 600WP's clock will depens on last frequency. Signed-off-by: Zhang Jiejing --- arch/arm/mach-mx6/cpu_op-mx6.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-mx6/cpu_op-mx6.c b/arch/arm/mach-mx6/cpu_op-mx6.c index 6f030102c821..60714dc7c8bf 100644 --- a/arch/arm/mach-mx6/cpu_op-mx6.c +++ b/arch/arm/mach-mx6/cpu_op-mx6.c @@ -36,8 +36,8 @@ static struct cpu_op mx6_cpu_op_1_2G[] = { .cpu_podf = 0, .cpu_voltage = 1100000,}, { - .pll_rate = 624000000, - .cpu_rate = 624000000, + .pll_rate = 672000000, + .cpu_rate = 672000000, .cpu_voltage = 1100000,}, { .pll_rate = 792000000, @@ -64,8 +64,8 @@ static struct cpu_op mx6_cpu_op_1G[] = { .cpu_podf = 0, .cpu_voltage = 1100000,}, { - .pll_rate = 624000000, - .cpu_rate = 624000000, + .pll_rate = 672000000, + .cpu_rate = 672000000, .cpu_voltage = 1100000,}, { .pll_rate = 792000000, -- cgit v1.2.3