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Clear error status register during init
Bug 1709814
Change-Id: I348526828015c84027b647bc728355ac9271a5fe
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/842868
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
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Don't panic in case of mselect error
Bug 1652598
Change-Id: Ia07380dae0c10cdea24a865046e7f6bbec7389bc
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/778344
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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The IRQ handler use drvdata, however drvdata was set *after*
registering the IRQ handler. If an IRQ fired before drvdata was set it
would crash the kernel. Fix this by setting drvdata before registering
the IRQ handler.
Bug 200081502
Change-Id: Id8578b2446b167d2b3131bc6f28820fc6f5d9e11
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/715722
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Implement Tegra WDT FIQ debug function.
Default is disabled.
Bug 1581432
Change-Id: Ic81ab4cd3285080016b37191e6e0fab18e330a30
Signed-off-by: Renn Wu <rewu@nvidia.com>
Reviewed-on: http://git-master/r/#/c/271988
Reviewed-on: http://git-master/r/662550
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Enables Simon graders if CONFIG_TEGRA_USE_SIMON is enabled.
Bug 1511506
Change-Id: Ie93bf0d5c7fbe9d6a60a3d2f2680b40a33c0f376
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/425052
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Simon graders that grade the CPU and GPU based on the simon state for
the specific simon domain.
Bug 1511506
Change-Id: I054ab8895e9d1773460c7ae9ba5f73191dd45e56
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/425051
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Allows for reading of the Ring oscillator frequency on the JTAG chain of
ROSCs. Performs the read via the APB2JTAG interface.
Bug 1511506
Change-Id: I6797f26c760e178f3d8dc4067b7d50bfce5086f0
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/425050
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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API to read and write from/to APB2JTAG chains.
Bug 1511506
Change-Id: Ib2b881cef9fd9a50e7fcc72c749045750f961008
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/425049
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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- The initilization of the mselect register was being done
against the hier_ictlr register base address, instead of
the mselect register base address. Correct the address
to the mselect register base
Bug 1519537
Change-Id: I2de684e26ff21b4034ed5493a5991e31d01b75c1
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/424959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
GVS: Gerrit_Virtual_Submit
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SW should explicity add delay between writes to IO_DPD_REQ and
IO_DPD2_REQ registers. This is because we use the same state machine
for both the registers.
The time between writes should be apb clk * (SEL_DPD_TIM + 5).
The worse case of apb clk is 32Khz,
SEL_DPD_TIM is configured as 0x10.
delay = (1/32000) * (16 + 5) which approximately 700us.
Bug 200002717
Change-Id: Icf4efdbc38ccdaca30a9d86da488ac796b657b36
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Reviewed-on: http://git-master/r/411065
(cherry picked from commit ebba7445ff9a32af6bb1759ac70311f66e2986cb)
Reviewed-on: http://git-master/r/412826
Reviewed-on: http://git-master/r/418379
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Move t13x edp params into its own file.
Clean up unnecessary core-edp constructs.
Change-Id: I215b52cfdd2db2f806e141e3b88a57492b17c0db
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/416798
Reviewed-by: Automatic_Commit_Validation_User
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Enable derating support on T132
Bug 1434354
Change-Id: I85afba374de1b75f37ef2a6dbf3752ab05f22ff9
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/416441
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Bug 1469388
Change-Id: If81cf0f73f10dc490c9bed3cbbb7e1875a9eff41
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/415618
(cherry picked from commit ef7f10628f8ae56a7a2c63400b286afe70f46a07)
Reviewed-on: http://git-master/r/415622
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Add MC error description for combination INVALID_SMMU_PAGE +
DECERR_VPR + DECERR_EMEM.
Bug 1500983
Change-Id: I37158c843ff534ab22f9ada0c66ae1d3d76bf650
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/412102
(cherry picked from commit ea8e9e5251c4bc24df93c4d964f7546569647972)
Reviewed-on: http://git-master/r/415240
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1469388
Change-Id: I1342e6a0cfdde83ee98163a0cc1080e5cf2e564a
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/413157
(cherry picked from commit 047713898790ec89daff11c90675497499ac2428)
Reviewed-on: http://git-master/r/413106
Reviewed-by: Steve Rogers <srogers@nvidia.com>
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Bug 1469388
Change-Id: I54cf4e56b0ee7041697a5bf373e9012bff789dc1
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/404025
(cherry picked from commit 54ff9f73e27a7d61f01a92bd8d887b9c4fc43ebe)
Reviewed-on: http://git-master/r/406403
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Change-Id: I06582980f2e9e88ab0e34bc5febc5d939fb77cc4
Reviewed-on: http://git-master/r/404934
(cherry picked from commit d1095251dadc17cb2c4f885f0d5d23359536f02b)
Reviewed-on: http://git-master/r/405472
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
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Bug 1443843
Change-Id: I140bf23b94d2948e639f781f40e5b198aa6f4fb6
Signed-off-by: Chao Xu <cxu@nvidia.com>
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/368894
Reviewed-on: http://git-master/r/404549
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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Bug 1469388
Change-Id: I020174ab09b008ddf36a6848eed9a3e25837d0b7
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/400176
(cherry picked from commit 4993c23beb775f696ccdda7b203b88a89a5bbf35)
Reviewed-on: http://git-master/r/402896
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Change-Id: Ife6926d0c00d7e046b2579795f50ef96d633fc8f
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/395845
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Remove some code that only gets compiled for tegra 3. Tegra
3 is no onger supported on main.
Change-Id: I8140f1613f93cef82b787ea7d67b5c3149e1c38b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/393046
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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At Aleks' request, change the name of struct tegra_tsensor_pmu_data, to
clarify what it is and what it does. This structure has nothing to do
with PMIC temperature sensors. Instead it's used to configure the boot ROM
appropriately to tell the PMIC how to power off the SoC after SOC_THERM's
critical thermal trip point has been reached ("thermtrip").
The name will now be 'struct tegra_thermtrip_pmic_data'.
Change-Id: I40e5aeeb74267993272e33c92300d3506a15a4a8
Cc: Aleksandr Frid <afrid@nvidia.com>
Cc: Diwakar Tundlam <dtundlam@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Reviewed-on: http://git-master/r/396170
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
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This reverts commit c2a9dbc2494b51ca7b50cb4fae6101c489a00873 since
it causes LP0 to be broken on T132 platforms.
Bug 1499478
Change-Id: If1279494cc10f647f1b7b84cfd6aeb88b8393e6c
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/395778
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
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Change-Id: I30baee4084399b8078232f31296c4d891a903d47
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/395123
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Adds DT support to the Tegra MC driver. This also removes the ability
to boot without a DT with a proper MC node. This may need to change.
Change-Id: I6d7fd7b333ae4a87e0d90b4c5f0d842837e4c638
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/325823
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Bug 1476459
Change-Id: Id96161878095ed927c7be3c69d1fbae245e36702
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/391780
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Refactor EDP code in preparation for adding T13x EDP support
(VDD_CPU and VDD_GPU) in order to reuse code that is common
between T12x and T13x.
Bug 1434482
Change-Id: I0a4fd70f9ae8fc4516d10250ed60cbbd502ce0f2
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/393656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
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Under certain conditions, the PMC can silently block writes into its
scratch registers. This can be a big problem when the values being
written are intended to shut down the PMIC after a critical thermal
shutdown event.
In this patch, we read back the PMC scratch registers to ensure that the
values contained therein are the ones we programmed. The code will
call WARN() if there is a mismatch. It probably should just shut down the
device.
Bug 1482109
Change-Id: Idb6c17a78c2b512114dbb0b2ad6615875ecbe5c4
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/392201
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
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The PMC IP block is not part of the SOC_THERM IP block, but the
SOC_THERM code contains direct register reads and writes to the PMC IP
block. Move these accesses into something PMC-specific: in this case,
drivers/platform/tegra/pmc.c.
While here, remove the usage of the REG_SET/GET* macros, since
upstream Linux practice is to use the actual bit-manipulation
operations, rather than these macros.
This is part of the process of modifying the tegra11_soctherm.c code
to convert it into a low-level device driver for the arsoc_therm IP
block.
We also relocate struct tegra_tsensor_pmu_data to a PMC-specific header
file, since it is PMC-specific, and convert any header references to the
old location to point to the new location.
Thanks to Matt Longnecker for comments on the first version of this patch.
Bug 1201644
Bug 1380438
Bug 1482001
Change-Id: Iea630ac9d9b3dfaab03edf44e2a2725174c7a3d8
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Diwakar Tundlam <dtundlam@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-on: http://git-master/r/392198
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
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Moving pm-irq.c from mach-tegra/ to drivers/platform/tegra/
as codes have to be shared between arm and arm64.
Bug 1440573
Change-Id: I91a071eca1fd5c578ae1087b8348e56f417c5bda
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/376552
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Moving pmc.c from mach-tegra/ to drivers/platform/tegra/
as codes have to be shared between arm and arm64.
Bug 1440573
Change-Id: Ic06c25d74fd2ca4d44eedd129ebcc71d8afa88f2
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/377302
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 1456092
Change-Id: I3021247ec68a3c2dddd9e98cde13d70a45191d53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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HSDISCON_LEVEL has be updated for detecting High speed devices
Bug 1454282
Change-Id: I857949807bfd3e21415eabccf6c085fd1a656cbb
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/377172
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Implement the necessary sysfs interfaces to expose the mselect timeout
as device attribute with +rw permissions.
Change-Id: I654823603d148cfee5d1f33d9373aebd7bafa474
Signed-off-by: Neil Gabriel <ngabriel@nvidia.com>
Reviewed-on: http://git-master/r/374430
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Marc Delvaux <mdelvaux@nvidia.com>
Reviewed-by: Sobby Thakalath <sthakalath@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Removing entry for timerinfo.o from the Makefile
because timerinfo.c is being migrated from mach-tegra/
to drivers/misc/ directory.
Bug 1380001
Change-Id: Ife427846a18c7fd43cad0bac1f7900a5698a7761
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/373431
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
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First draft or a new driver for the Tegra Hierarchical Interrupt
Controller. Enables and configures basic Mselect errors and interrupts
and hooks an interrupt handler.
Change-Id: I11c1987ad4fc6431b5d7f6948388d39c02279542
Signed-off-by: Neil Gabriel <ngabriel@nvidia.com>
Reviewed-on: http://git-master/r/366669
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Tested-by: Mitch Luban <mluban@nvidia.com>
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Let xusb can own ports with any combination.
Bug 1345723
Change-Id: I6532a44150bea1113ebee1483263158fb3c04117
Signed-off-by: Joy Wang <joyw@nvidia.com>
Reviewed-on: http://git-master/r/354888
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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To fix the T132 build. Regression from commit
2219ca8ed25b79ce07b20e4af7cf558c8525ae98
Change-Id: Ib995582ff54dbca00049134cf554d5bd238728aa
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/365173
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Left over after previous patch.
Change-Id: I2be9c0fccf6ff94c9bb820c7b84cf84d62da282e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/365125
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
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Move the MC driver out of mach-tegra and prepare the driver
for using the DT.
Change-Id: I544259de9e899b29152d7e2f08bce5745e40fb30
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/302984
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
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Change the permissions on a few files in drivers/platform/tegra
to not be executable since they are source files.
Change-Id: I116bc313c4ac73d879ff7567e2c29d083e63ae1e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/364070
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
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commit b0ad4ff35d479a46a3b995a299db9aeb097acfce upstream.
The DriveGuard chips on the new HP laptops are with a new PnP ID
"HPQ6007". It should be compatible with older chips.
Acked-by: Éric Piel <eric.piel@tremplin-utc.net>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Matthew Garrett <matthew.garrett@nebula.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Add missing files that was causing linker error for
64bit compilation
Change-Id: Id6ac994fd565756fef2b10850bc8c38b460f4978
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/360102
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
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Change-Id: I9a690aa36f19200ead704fdbe932b2ca6afd3aa7
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/351451
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
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Move mipi-cal to drivers/platform/tegra from mach
arch/arm/mach-tegra.
Bug 1408557
Change-Id: I4af7521cdbcf93c4926ca670e648bfdc562d279f
Signed-off-by: Rakesh Sharma <rasharma@nvidia.com>
Reviewed-on: http://git-master/r/350527
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
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Update Makefile and other supporting files for adding separate
dvfs and speedo files
Change-Id: Ifb7f9baa596a413164da7b3491f621820c9d9d88
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/350003
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
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Build board-ardbeg64-* files instead of board-exuma-* files for exuma_sim.
These same files will be used for the upcoming ardbeg64 build.
Change-Id: I69f3aa0658ffa88086fc99d481f282067a3ce7c0
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
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Update to ise the latest files in mach-tegra.
Change-Id: Ieb30f34135db458607a76b3563f98e02dd21e951
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
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The tegra fuse code has moved. Part of the move was to remove fuse.h.
Change-Id: Ied55e46e0a07f187316f0d97e69c8e528b37cb99
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
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Change-Id: Ide93d3ccc3463ebcac2417beeb252704b76a8977
Signed-off-by: Peng Du <pdu@nvidia.com>
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