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path: root/drivers/pinctrl
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2017-10-03pinctrl: tegra: clean-upMarcel Ziswiler
Cosmetic clean-up to bring it more in-line with mainline driver in order to be able to easily assess whether it is all kosher. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
2016-11-21pinctrl: tegra: fix some mistakes in Tegra124Stephen Warren
A couple of pairs of pin group names were swapped in the table. This caused the wrong register to be programmed. Luckily, this had little effect, if any, since the swapped pins were likely to be programmed identically. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> (cherry picked from commit 0ffdd4b61b1326b2b8a7c4fdf3c061d807be1a74)
2015-04-07pinctrl: tegra: Add MIPI pad controlBibek Basu
This patch adds MIPI CSI/DSIB pad control mux register from the APB misc block to tegra pinctrl. Without writing to this register, the dsib pads are muxed as csi, and cannot be used. The register is not yet documented in the TRM, here is the description: 70000820: APB_MISC_GP_MIPI_PAD_CTRL_0 [31:02] RESERVED [01:01] DSIB_MODE [CSI=0,DSIB=1] [00:00] RESERVED Signed-off-by: Sean Paul <seanpaul@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> BUG=chrome-os-partner:30799 TEST=Tested on ryu (cherry picked from commit 489c8251776de8838547207acce199f50846ded1) Change-Id: I424f488131e51ac793814d98d018162f0644509e Reviewed-on: https://chromium-review.googlesource.com/219832 Reviewed-on: http://git-master/r/668725 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/723409 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2014-12-01ARM: tegra: pinmux: correct clk3 & pcc1 groupBibek Basu
pcc1 & clk3_req_pee1 pins are moved to correct group Bug 1551864 Change-Id: Icf106aac866eec02afe7e703f879e5e7f6d722be Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/655140 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2014-09-15pinctrl: tegra: fix pinconfig_group_setBibek Basu
Prepare config using param parameter to generate the right value for pinmux register Bug 200033491 Change-Id: I973cc449e8cf89cb3b6f5b5da1021d21d193b47d Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/496827 (cherry picked from commit 418c027e40353a4b99fe7fcfbc0743de7e07d15c) Reviewed-on: http://git-master/r/498329 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2014-09-15pinctrl: tegra: set tristate =1 and input =0 for unused pinsLaxman Dewangan
Set the tristate bit to 1 and e_input to 0 for unused pins to set it on low power and avoid conflict with any other pins. Bug 200033491 Change-Id: If83f6129dbf6c6fe28a7a7c596e5a3858a894914 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/416649 (cherry picked from commit 7e81b36f87cffdc5d473a39735877a1432ac3151) Reviewed-on: http://git-master/r/498328 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2014-09-15pinctrl: tegra: configure pins for gpio directionLaxman Dewangan
If pin is configured on gpio mode and set for input direction then set e_input = 1 and if pin is set for output direction then set tristate = 0 for that pin. Bug 200033491 Change-Id: Ibcae17ad8bf4e45f0c74eb68d3bf975078fb67d6 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/416650 (cherry picked from commit 3dbac8e8382be0766e221c3f47f6254538b17030) Reviewed-on: http://git-master/r/498327 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
2014-06-23pinctrl: tegra: fix tegra_pinctrl_disableKerwin Wan
The value written to mux_reg should be from 0 to 3 to select the proper function. Change-Id: Ie056189332c839588eeca1d210f264482a73995a Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/426477 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit
2014-04-23pinctrl: export API for pinctrl_get from devname/ofLaxman Dewangan
Export the pinctrl API for pinctrl_get() based on dev-name and device node handle. This helps on getting pinctrol handle to client so that client can modify the pin configuration dynamically. Change-Id: I5acca29f8467d61503b2dc079f4a520415052ff2 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/394786 GVS: Gerrit_Virtual_Submit
2014-03-18pinctrl: pinconf: Use correct return typeShravani Dingari
Use correct return type for pinconf_dbg_config_write() api Change-Id: Ibb2e5beffd98535dc71f3d63f72e9f1749799829 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/382410 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-03-13Merge branch 'linux-3.10.33' into dev-kernel-3.10Deepak Nibade
Bug 1456092 Change-Id: I3021247ec68a3c2dddd9e98cde13d70a45191d53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
2014-02-20pinctrl: protect pinctrl_list addStanislaw Gruszka
commit 7b320cb1ed2dbd2c5f2a778197baf76fd6bf545a upstream. We have few fedora bug reports about list corruption on pinctrl, for example: https://bugzilla.redhat.com/show_bug.cgi?id=1051918 Most likely corruption happen due lack of protection of pinctrl_list when adding new nodes to it. Patch corrects that. Fixes: 42fed7ba44e ("pinctrl: move subsystem mutex to pinctrl_dev struct") Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-20pinctrl: vt8500: Change devicetree data parsingTony Prisk
commit f17248ed868767567298e1cdf06faf8159a81f7c upstream. Due to an assumption in the VT8500 pinctrl driver, the value passed from devicetree for 'wm,pull' was not explicitly translated before being passed to pinconf. Since v3.10, changes to 'enum pin_config_param', PIN_CONFIG_BIAS_PULL_(UP/DOWN) no longer map 1-to-1 with the expected values in devicetree. This patch adds a small translation between the devicetree values (0..2) and the enum pin_config_param equivalent values. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-17pinctrl: tegra: add syscore save/restore functionsPrashant Gaikwad
We need to save PINCTRL state when going in LP0 from idle. Syscore save/restore are called from idle thread before going in LP0 while suspend/resume are called in case of system suspend LP0. Bug 1254633 Change-Id: I806d70b989614056a857e847d3a2ebdcb0e03959 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/367579 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-11pinctrl: as3722: add support for setting output valueLaxman Dewangan
Add support for setting the pins in output mode with state from generic pinconf DT properties output-high and output-low. bug 1444223 Change-Id: Id263779e4e797bb1d1ad1744b272a896a857c695 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/365887
2014-02-11pinctrl: tegra: ignore string case in debugfs writePaul Walmsley
Ignore the case of the string in debugfs pin remux writes, for the convenience of those debugging the system. So either echo "HDMI_CEC CEC OUTPUT NORMAL TRISTATE" > /d/tegra_pinmux or echo "hdmi_cec cec output normal tristate" > /d/tegra_pinmux should work. Bug 1434110 Change-Id: I04132445e81b63a39a6ae0a1595d0bbac7c099c9 Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Laxwan Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/364882 GVS: Gerrit_Virtual_Submit Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-11pinctrl: tegra: fix debugfs field delimiterPaul Walmsley
The delimiter between pinctrl fields should be a space, not a newline, except for the final field on the line. That field should be terminated with a newline. Without this patch, the example in the code comments before dbg_pinmux_write() would need to be something like /bin/echo -e "HDMI_CEC\nCEC\nOUTPUT\nNORMAL\nTRISTATE" > /d/tegra_pinmux rather than the stated behavior: echo "HDMI_CEC CEC OUTPUT NORMAL TRISTATE" > /d/tegra_pinmux Bug 1434110 Change-Id: I5bacaf8c6c89afc7d51201455e670bbb172cea87 Fixes: 688ad54fa90f178025e9392b2b3a5f9ec92bfab5 ("pinctrl: tegra: add APIs to access pincontrol from non-dt driver") Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/364881 GVS: Gerrit_Virtual_Submit Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2014-02-06pinctrl: sunxi: Honor GPIO output initial vaulesChen-Yu Tsai
commit fa8cf57c923e86a693a85aff1df579245a27cbb3 upstream. Some GPIO users, such as fixed-regulator, request GPIO output with initial value of 1. This was ignored by sunxi driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-04pinctrl: tegra: add register base address and group name when dumpingLaxman Dewangan
Add the register base address in the offset and group name when dumping register content. This helps on quick reference of the content of register and relate to the pin. Change-Id: Ib14d6230109ca16f3c889ffd97f9182581607fd0 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/363249
2014-01-30pinctrl: tegra: fix drive groups configuration handlingLaxman Dewangan
For Tegra124, all drive groups does not supports all configuration. The configuration which is not supported is having the bits as -ve in their pinconfig table but related variable is declared as unsigned making this configuration as valid. Correct the datatype of the drive groups configuration bits and handling this properly across the driver to ignore the configuration which is not supported. Change-Id: I9b5666f7fa966df05df566196d155b516cded629 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/361999
2014-01-09pinctrl: as3722: set pin mode to outputMallikarjun Kasoju
If pins are used for function output like pwm, clk32k, power good etc then set it as output mode by default. Change-Id: I3ec3066f34c8a360f55bf6187f177509f79c6c06 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/349796 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/352238 Reviewed-by: Automatic_Commit_Validation_User
2014-01-03ARM: tegra: pinmux: correct pinmux resume sequenceMohan T
Do not operate on DPD pads and do not TRISTATE pins before restoring for T124 Bug 1416263 Bug 1429819 Change-Id: I7261c7e5d4341f6d74dadf1ab6af985e7965b860 Signed-off-by: Mohan T <mohant@nvidia.com> Reviewed-on: http://git-master/r/351369 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com>
2013-12-16Merge tag 'v3.10.24' into HEADAjay Nandakumar
This is the 3.10.24 stable release Change-Id: Ibd2734f93d44385ab86867272a1359158635133b
2013-12-09pinctrl: tegra: add missing string seprator for group entriesLaxman Dewangan
Add comma(,) after each entry in groups as string separator. Also remove non-required line and move MODULE_DEVICE_TABLE for "of" to proper location. Change-Id: I048fbae5a57fed0814a2b5153ce9e94e6ff19406 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/339883 GVS: Gerrit_Virtual_Submit
2013-12-09pinctrl: tegra: fix the pincontrol group entries for T124Laxman Dewangan
Correct pingroup entries for T124 pincontrol tables. Change-Id: I490d2e79011e415ac03413db73e9bc8aed2e207d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/339204
2013-12-09pinctrl: tegra: set pins into suspend state before entering into suspendLaxman Dewangan
Set the pins into suspend state before entering into suspend. The suspend state of pins are provided through DT. bug 1419765 Change-Id: I2765fa8f2135e2b72d82ba875b83be06b5f93929 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/338725
2013-12-04pinctrl: dove: unset twsi option3 for gconfig as wellRoel Kluin
commit 6d0a4ed2b90a12e1403d3e7d9d8c2cc7fdc301b5 upstream. This fixes a typo which left twsi config3 option enabled. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-11-28pinctrl: tegra: configure user state pinmux expliclty during probeLaxman Dewangan
Define two pincontrol user states, drive for drive group settings and unused for setting unused pins in low power states. Confgure these states during probing of pincontrol driver. Change-Id: I144b03ce6fa1f377b7f01c2b64ec1d8dd8899ffd Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/336160 GVS: Gerrit_Virtual_Submit
2013-11-28pinctrl: tegra: add debugfs for dumping pincontrol registersLaxman Dewangan
This will help the debugging of pincontrol by matching with register settings. Change-Id: I8af731b3208c7d0786d9c7ea18e2b758f33b1058 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/336159 GVS: Gerrit_Virtual_Submit
2013-11-28pinctrl: core: add support to configure user specified statesLaxman Dewangan
Currently, pincontrol driver defines three states i.e. default, idle and sleep. The default state get sets when the pincontrol driver gets regsitered. In tegra boards, we define three types of default, commpn pinmux table, driver setting table and unused low-power pins pinmux tables. Add the API to support the user specified state names to configure the pinmux. Change-Id: I0a6a234e891b5d53dbb8996db47984323463da48 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/336158 GVS: Gerrit_Virtual_Submit
2013-11-28pinctrl: tegra: add safe pinmux function optionLaxman Dewangan
Add "safe" as the valid pinmux option from the DT. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: Ic09de7b2f521df45c5d00d7267689d36c1c8479a Reviewed-on: http://git-master/r/335020 GVS: Gerrit_Virtual_Submit Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-11-26Remove writable permission for pinmuxLeavitt Zhang
To pass CTS 4.3, which guarantees that all files under /sys are not writable for others. Change the flag when creating tegera_pinmux. Bug 1389582 Change-Id: Iac77fdc87dc9a7be7dd74e75f94656c9080855bb Reviewed-on: http://git-master/r/335503 Reviewed-by: Lin Zhang (SW-TEGRA) <leavittz@nvidia.com> Tested-by: Lin Zhang (SW-TEGRA) <leavittz@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-11-22pinctrl: tegra: use pinmux define header onlyLaxman Dewangan
The data type definitons of tegra pinmux is in mach/pinmux-defines.h and so including this file only instead of mach/pinmux.h Change-Id: I8d373e0d8e3ea8f7c39b4d008d79f5c4660ef0c1 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/333435 Reviewed-by: Automatic_Commit_Validation_User
2013-11-19pinctrl: tegra: Change SAFE option of some of pins to new reservedLaxman Dewangan
Change safe option of some of pins to proper reserved option and fix the device name for sdio1 drive group. Change-Id: Id6b773e35cf3f1b55849743648d1675eae57da2b Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/332803 GVS: Gerrit_Virtual_Submit
2013-11-19pinctrl: tegra: fix string comparision compilation warningLaxman Dewangan
Fix following string comparision warning: /** pinctrl-tegra114.c: In function 'tegra114_pinctrl_suspend': pinctrl-tegra114.c:2817:32: warning: comparison with string literal results in unspecified behavior [-Waddress] **/ Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I3e059bd916534c30b1f5e1b56f0ac947b896a102 Reviewed-on: http://git-master/r/332802 GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-11-19pinctrl: tegra: set drive_type width to 2 for tegra114 pincontrol table.Laxman Dewangan
Change-Id: If4bf33b41ee8bf463743bc31a5f23e42d9ff654e Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/332801 GVS: Gerrit_Virtual_Submit
2013-11-19pinctrl: tegra: return drive group ID from drive_get_pingroup()Laxman Dewangan
Return the drive pingroup ID from the function drive_get_pingroup() when device name found in drive strength table otherwise return error as -EINVAL. Change-Id: I6e5ce1316d210941dea00e3f17e3bce5b65bf683 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/332800 GVS: Gerrit_Virtual_Submit
2013-11-19pinctrl: tegra: print group name in error msg when setting pinconfLaxman Dewangan
Change-Id: I6293b23374b648f08adea6641833e71060b2a07d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/332799 GVS: Gerrit_Virtual_Submit
2013-11-18pinctrl: tegra: fix the ddc_pin control register addressLaxman Dewangan
The DDC_SCL pin control register is placed at 0x3114. bug 1409300 Change-Id: Ie39dea7d915845ebed5c2914d4f717d141c8195c Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/332418 Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
2013-11-13pinctrl: tegra: fix the debugfs pinmux dumpLaxman Dewangan
Change-Id: Ib0876549714964fba925b34da272488fc997329d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/330357 Reviewed-by: Automatic_Commit_Validation_User
2013-11-13pinctrl: tegra: correct entry of pingroup gpio_w2_aud_pw2Laxman Dewangan
Set the pingroup gpio_w2_aud_pw2 safe option to RSVD2 as per valid option. Change-Id: If1427c04830732050d7bbb2b56870333f0bed069 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/330217
2013-11-13pinctrl: tegra: rename public API to refelct that it take pg enumLaxman Dewangan
The Tegra pincontrol public API for not-dt support can be called with pingroup enum option as well as the pingroup name option. Rename the API accordingly to reflect this. The calls for pingroup name will be added later. Change-Id: I6f2bd629088e7e903afea34c2a073f50f6cfafe1 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/330170
2013-11-13pinctrl: tegra: t114: update resume sequenceAshwini Ghuge
Tristate pins and write IO_DPD regs before restoring old pin state. Clear DPD_SAMPLE after restoring old pin state. Add NOR boot fix, to tristate GMI_WR_N pin before suspend. Change-Id: I44a5f632ac1f8dbc643ca3ee05a165bbfba3c724 Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> Reviewed-on: http://git-master/r/328209 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-11-13pinctrl: tegra: do not initialise the drive type if it is not supportedLaxman Dewangan
Tegra124 do not support the drive type and hence initializing only for Tegra SoC which support it. Change-Id: Ib09a17df05008ac50e704243736aaaf8b8183bf4 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/329991 GVS: Gerrit_Virtual_Submit
2013-11-13pinctrl: tegra: correct pincontrol driver group name for soc table.Laxman Dewangan
Correct the pincontrol driver group name of Tegra114 and Tegra124 on soc specific initialisation table. Change-Id: I3af8028aae3edfaade727a41f8c7c94ca4e859f2 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/329990 GVS: Gerrit_Virtual_Submit
2013-11-11pinctrl: as3722: add non-dt supportLaxman Dewangan
Add non-dt support for AS3722 pincontrol driver so that default pin configuration can be passed through platform data during registering of driver from board files. Change-Id: Ia14c709f84f45f7a994435c980386f4ed11e0ad4 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/328686
2013-11-10pinctrl: tegra: correct mux status checkAshwini Ghuge
Return error only on mux less than zero Change-Id: I3a6a36c20e64a302a51f8b79476b05dbe3a5142a Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com> ldewangan: remove un-necessarily change. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Change-Id: I8662164ab168a11e4b557334aa7bdcd5ceb88ae5 Reviewed-on: http://git-master/r/328684 Reviewed-by: Automatic_Commit_Validation_User
2013-11-08pinctrl: tegra: add drive initialisation table for Tegra124Laxman Dewangan
Change-Id: I02868b173040a3c93158f59c9b69842e2b56d88c Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/327756
2013-11-08pinctrl: tegra: add drive initialisation table for Tegra114Laxman Dewangan
Change-Id: Ida0d652c227b18f89b9d50ed5af33cadf569ea83 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/327755
2013-11-08pinctrl: tegra: add support for soc specific drive configurationLaxman Dewangan
Every soc have their default driver configuration based on characterization recommendation. Add support to configure the drive group during pincontrol driver initialisation. Change-Id: I9af34c65feb77a5bb8af15a08dffe246e8c8eb9d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/327754
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 01:20:37 +0000