Age | Commit message (Collapse) | Author |
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Fix a type of flag of disabling HS200 mode on tegra sdhci.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
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As stated by the eMMC 5.0 specification, a chip should not be rejected
only because of the revision stated in the EXT_CSD_REV field of the
EXT_CSD register.
Remove the control on this value, the control of the CSD_STRUCTURE field
should be sufficient to reject future incompatible changes.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 03a59437ef6b6ad7fb0165cb9b96c08d6bf057fc)
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Merge NVIDIA's latest Linux for Tegra aka L4T R21.6 Linux kernel changes
from git://nv-tegra.nvidia.com/linux-3.10.git commit:
b271e8fa67a6d9c4600274a25636cfe00fdd1b68
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
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This reverts commit 0293e897d740cc7991c82567aab5dee0e66294fd.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
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Now with the working card detect pin in place on the latest V1.1 HW
polling is no longer required. Therefore make it an optional define for
V1.0 samples.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
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As we limit the clock to 200 MHz also add tap hole coefficients to
allow for successful UHC-I tuning on SDMMC1.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
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Bug 1779090
Change-Id: I733c6ff7b3e39216fcf25f9c0d048b4c752a9e84
Signed-off-by: Anubhav Jain <anubhavj@nvidia.com>
Reviewed-on: http://git-master/r/1173092
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Allocate buffer with 1 extra byte for NULL terminator.
Bug 1791602
Change-Id: I3c3658315c2cd2a1dc7be7d72953998a5275e71e
Signed-off-by: Xia Yang <xiay@nvidia.com>
Reviewed-on: http://git-master/r/1216897
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
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Disable the external loopback and use the internal loopback as per
SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to
0xfffd according to the TRM.
Enable card detect polling as we can't use SD1_CD# aka
SDMMC3_CLK_LB_OUT for now as it features some magic properties even
though the external loopback is disabled and the internal loopback used
as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set
to 0xfffd according to the TRM!
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
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This reverts commit ca90caa335e3ded32ad6b0a92ad0fa00b67b2322.
We do require eMMC hardware area boot partition access for fw-util aka U-Boot
envrionment access.
Signed-off-by: Dominik Sliwa <dominik.sliwa@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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As stated by the eMMC 5.0 specification, a chip should not be rejected
only because of the revision stated in the EXT_CSD_REV field of the
EXT_CSD register.
Remove the control on this value, the control of the CSD_STRUCTURE field
should be sufficient to reject future incompatible changes.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 03a59437ef6b6ad7fb0165cb9b96c08d6bf057fc)
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tuning best_tap_value at times throws wrong value leading
to data crc error. To make the SW robust, reverify tuning
best_tap_value with previously calculated and then only
proceed.
Bug 200107220
Bug 200102727
Change-Id: If58194bcfd1f025b15f827b233b534b8fc999327
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/761054
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Tested-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit 6ad6591bf83670f91ab5f7628b5a6c3db3e9da4c.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: If31a8a2a53a804657ebc5878be8594230acba2aa
Reviewed-on: http://git-master/r/759477
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit f9b36d3b89f76cc48678eeb7a27cb980e89901d0.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: Ie862afeda5e7e5b360775248fbbc49a031528a0b
Reviewed-on: http://git-master/r/759476
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit 3c5f4d1060669ec73dc0ceb4e9a876a55a89c5eb.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: Ic0e3eb4bb892e69dbd808c1d55721290c561ac7c
Reviewed-on: http://git-master/r/759475
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit af2031797899b32504e32af377fa65875c06a746.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: I21c89606f1eed0e7d4445c5dfcf7e6d2382829e7
Reviewed-on: http://git-master/r/759474
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit 8eadba170693964dc30b1e6ab0a80df012858bc0.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: Icd990d1e9c8df4c66c46e7e29a03cc6233e206bd
Reviewed-on: http://git-master/r/759473
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit 28c9354b7cbade8813e0e5dbe9937300219fbeb9.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: I4a809d75523513c939fa17a6dbeebee292aec77b
Reviewed-on: http://git-master/r/759472
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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This reverts commit 0bb08ee76692a7ded9fb063b3bd77e1848658ced.
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Change-Id: I83df90d63845bc17bc1a4bf9d28cd47ac60fe9bd
Reviewed-on: http://git-master/r/759471
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
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For removable devices, check for the card presence status before
issuing each tuning command. If the device is removed, abort tuning
and return -ENOMEDIUM error.
bug 1625262
Change-Id: I19d5dfe8e8bf4b9fc7ecc2c00cdfa01343012e68
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/398855
(cherry picked from commit 6e82d03dca5b421138e1c4f348efee71df2a865f)
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/721906
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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bug 200007291
Change-Id: Ia1d8d4c8ea67a30c61e4178863e2f6f1bcb13753
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/413049
(cherry picked from commit 7564df85908c98b8fd6e5835cb02262091057d4e)
Reviewed-on: http://git-master/r/725517
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeetesh Burman <jburman@nvidia.com>
Tested-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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bug 200035711
Change-Id: I2efdabe31ec2ab5b6b0253f54484365e61890e91
Signed-off-by: Seshagir.H <sholi@nvidia.com>
Reviewed-on: http://git-master/r/538920
(cherry picked from commit ef940296b6f41e4669fe7da4c48bf34091af2512)
Reviewed-on: http://git-master/r/725516
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jeetesh Burman <jburman@nvidia.com>
Tested-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Initialize tap hole variables used in the temperature margin
calculations.
Bug 1532100
Change-Id: I494d5ab1600f13c8861de860532021107bfd745e
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/436633
(cherry picked from commit a106c31d73581db47c951b8cc196629993b96571)
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/721901
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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-To derive estimated tuning data for other than boot_mv and vmin
we are using precision of 1000.
-Use precision of 100000 to derive data more accurately
Bug 1414513
Change-Id: I9caff04515980713a83f33c4cf6b524ba022d2b8
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/437992
(cherry picked from commit 36330ecf4ffe9333bf895f2e943f8b6b7201c012)
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/721897
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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-disable card clk.
-update the tap value.
-enable card clk.
Bug 1559166
Change-Id: Ib77bfed5d8a8569d458aaf2cd0cd3c8a9e00a60e
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/559812
(cherry picked from commit e2c098821a74ef1b5805c6bc5cb177a4fba05338)
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/721896
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Avoid false warnings by reporting missing fixed tap hole margins only if
NVQUIRK_SELECT_FIXED_TAP_HOLE_MARGINS is set rather than printing the
message unconditionally.
bug 1625262
Change-Id: Ie5b75f3f73c6ce7e6283912f9ee41ae4d5d68901
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/599356
(cherry picked from commit 8f676f54519fa169c12f384ded3df1d6a87e8fd5)
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/721846
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
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Added DVFS support for CD575M Always on behaviour.
With this personality configuration for the chip,the
lifetime of the chip increases to 5 Yrs
Operating Temp : -25 to 105 degC
CPU DVFS: Max Freq 1938Mhz. Max Voltage 1.12V
SOC DVFS: Max Voltage0 1.01V EMC dvfs max freq 792Mhz
GPU DVFS: Max Freq 804Mhz and Ma Voltage 1.09V
Bug 1563635
Change-Id: If7fec38b83ae4de8c5435006207fa3cf717384c0
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/594855
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Initialize uninitialized variable
vmin_tap_hole & vmax_tap_hole
Bug 200042035
Change-Id: I5e9303f2b585423d936b289a59228028275ec5ec
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/542582
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Currently, there is no binding for coherent_dma_mask and dma_mask
in device tree. If sdhci-tegra driver is probed from DT,
coherent_dma_mask will be set to 32 bit as DT default and
dma_mask will be NULL.
So added coherent_dma_mask setting for each Tegra SKUs.
And if dma_mask is NULL, set it to coherent_dma_mask.
Bug 200000521
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/433116
(cherry picked from commit 4b624565615f4f549a556ac7cbf1957cc8d978d5)
Change-Id: Id78e3d225619fb232e10cf957502aea4a131063a
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/433893
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
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This patch adds tap hole coeff for 200MHz for SDMMC3,
for tegra12x
Bug 1505798
Change-Id: I54de2a7529952367e361d8bd55a669335142193f
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/412543
(cherry picked from commit f2a9fc57238de62bc996f7565850b7012e1f5962)
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/422035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
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Use pre-allocated DMA buffers for ADMA descriptor and Bounce buffer
instead of dynamic DMA mapping.
This improves SDHCI driver performance by reducing dynamic DMA mapping
overhead.
Bug 1486735
Change-Id: Ic9c646437be047d33304339eccc48a825f0a8bcc
Reviewed-on: http://git-master/r/380885
Cherry-picked from commit 7ffcc4cf1a1cec42610c1b55c30b3ec28547a11e
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Change-Id: If850a534ba9fbfd169b4fbefd35ca5922b1d1254
Reviewed-on: http://git-master/r/416955
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: R Raj Kumar <rrajk@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
(cherry picked from commit 9e58888afe4e66e83eece0a8332c8e7440bd1bcf)
Reviewed-on: http://git-master/r/419444
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If dvfs overrides are disabled, continue tuning execution by
treating the dvfs override API return values as expected.
Bug 1516198
Change-Id: I8d27969029ce7b318d23c227e8dfb19793282fea
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/413118
GVS: Gerrit_Virtual_Submit
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
(cherry picked from commit 71edeee1a98a8dc7474781689b0859a32f5aca80)
Reviewed-on: http://git-master/r/419948
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Wake irq enable/disable is done from
suspend/resume instead of probe/remove
bug 992448
Change-Id: Ic5fa9bad39aa176ab07f794c5c75031cb11a3273
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/410435
(cherry picked from commit a96a3af02eed790174b0f03e954f0057ae2c0091)
Reviewed-on: http://git-master/r/415373
Reviewed-by: Automatic_Commit_Validation_User
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Reset Data lines just before cmd line reset.
Bug 1478949
Bug 1437140
Reviewed-on: http://git-master/r/387439
(cherry picked from commit a86596118aef274ee378cd0884948b6d7fe039f5)
Change-Id: I58244d005e6f44eaee5b1b1e264f2f6cccb35054
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/411302
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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While trying to dump all sdmmc files debug data, on TN8,
card is not present on few sdmmc controllers resulting in
null pointer access. This change fixes this by adding check.
bug 1508535
Change-Id: I4ce6ff7b95b81e53684aed2602f932d6214f1221
Signed-off-by: Prafull Suryawanshi <prafulls@nvidia.com>
(cherry picked from commit 6a17f1ac0f24e6d9e2218d4ea3f32db784ffd1e5)
Reviewed-on: http://git-master/r/406766
Tested-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/410175
Reviewed-by: Mitch Luban <mluban@nvidia.com>
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Before sdhci set_ios call we need to flush
outstanding delayed clock gate work. Else,
it could cause unintended clock gate
resulting in hard hang.
- unconditionally cancel delayed clock
gate work since sometimes mmc->card->type
is uninitialized.
bug 200000303
Change-Id: I208a8a15dfd4f8d8ae1614d0fadee6deb5a55bb0
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/407407
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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During mmc rescan the attach sdio call could
fail. The sdio host clocks are turned Off as
part of error handling. Use power up to
turn clock ON. power down call is needed
since subsequent calls in consecutive power up
return immediately.
bug 1456241
bug 200000303
Change-Id: I6c412ded8e15bc07af93750cb25ac71fee483021
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/402435/
Reviewed-on: http://git-master/r/402969/
Reviewed-on: http://git-master/r/402980
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Fix Coverity issue of possible memory leak
Coverity id : 25731
Bug 1416640
Change-Id: I3aed6d423bfb048c35470048a90b55883f39f482
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/398109
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Need different drive type modes for different board’s.
So implement drive strength selection call back and
provide the drive type mode from platform here.
Bug 1458921
Change-Id: I2e21eadfaeb592ba92c424bfa11f9a7dd64cdb51
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/395843
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Each platform has different requirements for
drive strength based on trace length and other
phy parameters. So implement the drive strength
call back for host controller driver to get
drive strength.
Bug 1458921
Change-Id: I38007a147bc8111160b3360c7c33167c795ceb54
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/395842
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
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Corrected delayed clock gate timeout expression
for cases where kernel time to switch between
processes is more than 10msec.
bug 1496751
Change-Id: I7fbb670a932b690f521ff1205dce3b81d60a51c2
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/393886
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
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Do not ignore parent clk setting and parent clock source flag
update for any case. For eMMC, in resume, without pll_c as clk
source, 200MHz cannot be set in HS200 mode set.
Bug 1480583
Reviewed-on: http://git-master/r/389704
(cherry picked from commit b9b0cb1541d66ba2450a680666c3fe962b4f71df)
Change-Id: I7898a57871cd16de49142a6534a998bef0c43529
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/395205
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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-use pr_info instead of pr_err
-best tap value is an information and not an err
hence changing to pr_info
Bug 1492481
Change-Id: I34d8634ae1e358d3c227a1101f8ae9f7f87627a0
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/395639
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: I30baee4084399b8078232f31296c4d891a903d47
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/395123
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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-Enable SDHCI_QUIRK2_HOST_OFF_CARD_ON flag.
-VERSION_4_EN bit and 64BIT_EN bit are cleared during suspend
need to re-configure them.
Bug 1487250
Bug 1479825
Change-Id: I63b5256f4ba8e9d262e2108e2f1022d9287674ed
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/392296
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
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-use dev_info instead of dev_err
-best tap value is an information and not an err
hence changing to dev_info
Bug 1492481
Change-Id: Icf8cc4168d9cab8e121355814c66ece2b2230531
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/391306
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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For devices that are always powered on, run calibration in
platform resume. The resume path for these devices primarily
restores host context and doesn't call any signal voltage
change APIs. This patch ensures that calibration is done
during resume and proper drive strength codes are applied.
Bug 1423429
Reviewed-on: http://git-master/r/383825
(cherry picked from commit 17ba4fd032b349626e20fd606ed5caa4a515ff67)
Change-Id: Iaae2fba42395a2b783bcac06e3141842340c4e50
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/389577
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Send signal voltage value to auto calibration code
Bug 1423429
Reviewed-on: http://git-master/r/383824
(cherry picked from commit 7eecf6e511c6462625781ef70815076826fbec92)
Change-Id: I87b633425ac30f167df0637b743f7962821fc240
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/389576
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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Sanitize cmds have very long busy wait times. Increasing the SW timeout
timer for sanitize cmd to ensure that the driver doesn't trigger
timeout in the middle of sanitize busy wait.
Bug 1385731
Bug 1392724
Bug 1484117
Reviewed-on: http://git-master/r/303361
Change-Id: Ibb73b27159508b2ae851032a6ea1432f76b1f384
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/384773
(cherry picked from commit 021b596219b1f2ca280e239a8a8e64a3e8802ac8)
Reviewed-on: http://git-master/r/386119
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Kerwin Wan <kerwinw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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In case of SDR104/SDR50 modes, set tuned tap value if tuning
is already done.
Bug 1469287
Change-Id: I94f564f2c3490e1ffcc6c2acc2159d7d71d1a189
Reviewed-on: http://git-master/r/381505
(cherry picked from commit f4ef9870d1dd610e3ec69cae4ca6cef1de40e98e)
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Philip Rakity <prakity@nvidia.com>
Reviewed-on: http://git-master/r/382321
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
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