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2014-04-13platform: tegra: move pm_domain to driversPrashant Gaikwad
Change-Id: I30baee4084399b8078232f31296c4d891a903d47 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/395123 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2014-01-22crypto: tegra-se: Fix data type mismatchShravani Dingari
Handle distinct data type (size_t and unsigned int) comparison Bug 1414788 Change-Id: Ia9f8255eb447bb0bc82ec48218aa2c77e167c5c1 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/340287 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
2014-01-16crypto: tegra-se: fix resourse leakSalona Sinha
Coverity id : 25364 Bug 1416640 Change-Id: I6cbdc67004f94f2afbc4c8b656631f4d4a0ce8c5 Signed-off-by: Salona Sinha <salonas@nvidia.com> Reviewed-on: http://git-master/r/356025 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-12-19crypto: tegra-se: fix allocation failureHiroshi Doyu
This is the fix for: "crypto: tegra-se: avoid ctx save buf from highmem" when it causes allocation failure because of OOM. Bug 1414172 Bug 1427490 Change-Id: I3287849f2d144b131d413e16cc410ff13ab7ad05 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/346861 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
2013-12-12crypto: tegra-se: Add DT supportShravani Dingari
Add DT support for SE driver Bug 1369830 Change-Id: Iebd0a7f58d0ee6eb3ebc7f75f81690bc1ec972c0 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/334930 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-12-12crypto: tegra-se: avoid ctx save buf from highmemHiroshi Doyu
DMA API(IOMMU) can allocate pages from highmem since IOMMU usually voids the limitation of accesible page range from HWA. But there's some special case that a client wants pages accessible within 32bit explicitly, especially for some PM suspend/resume case here. This patch gives a hint to DMA API where to allocate pages. Bug 1414172 Change-Id: I4f457264724d92e2d9fba7993c2c62c165fe2010 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/343646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-12-12Revert "crypto: tegra-se: alloc ctx save buf from atomic pool"Hiroshi Doyu
This reverts commit 08b47b078d9cccc831d23eeeabaeec18f51c562c. Bug 1414172 Change-Id: I5050f886aa9e3bc4cdc508f52204506543dfdef4 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/343644 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
2013-12-09crypto: tegra-se: Support RSA Context Restore testShravani Dingari
Support for RSA Context Restore test and also allocate RSA key slot only if it is not done for current context Change-Id: I50c9f3fca6c189a17d07ba3325118a0fa6e13906 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/299945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-11-15crypto: tegra-se: alloc ctx save buf from atomic poolKrishna Reddy
dma_alloc_coherent allocates from high memory as well. With this, phys addr is not guarnateed to be <= 32-bit. Use allocation from atomic pool as WAR. Bug 1396209 Change-Id: I8730af614c8e4fc5af10f75ecaefd72feb5d278d Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/329912 Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: David Dastous St Hilaire <ddastoussthi@nvidia.com>
2013-09-16crypto: tegra-se: Compile RNG code conditionallyShravani Dingari
Compile RNG related apis only for T30 SOC Bug 1275788 Change-Id: I766328c2d08e7c131b46a3b770d72cbfc852aae7 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/268458 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-09-14ARM: tegra: Move platform detect from <mach/hardware.h> to <linux/tegra-soc.h>Dan Willemsen
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: I13f3ff891510d2c868f609d507149b32183d34c5
2013-09-14crypto: tegra-aes: Revert to v3.10.10 versionDan Willemsen
This isn't being built on supported products, so use the upstream version. Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com> Change-Id: If2abf074dcf702062eb8c2bcf7c3cb79bb5ae354 Reviewed-on: http://git-master/r/270000
2013-09-14crypto: tegra-se:Correct RSA context save sequenceShravani Dingari
While saving LP0 context, save RSA modulus first and then RSA exponent Bug 1346862 Change-Id: Ib3c6d30cb492c112dcfef5128399d5fe807e8129 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/264776 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-09-14ARM: tegra: Call tegra_se_suspend to save SE contextShravani Dingari
Call tegra_se_suspend() again, immediately after returning from tegra_suspend_dram(), during LP0 exit. To call se_suspend(), tegra_smmu_resume() also needs to be called. This is an attempt to regenerate SRK and SE context, so that BootROM won't kill SE on LP0 exit ( if we try to re-enter LP0 early without waking to active). Bug 1234330 Change-Id: Ib71e0c9972f307e48395b8f16d79867ad95659a0 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/243462 (cherry picked from commit 155aef2ee1ce6cf0481f8419809024f3e4e7c0e9) Reviewed-on: http://git-master/r/250052 Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-09-14crypto: tegra-se: Remove condition to enable SE clockShravani Dingari
Enable SE clock even if it is fpga platform Bug 1271895 Change-Id: I461dbf44a597eeda3fe940c775f0f131b55da52a Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/241873 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14crypto: tegra-se: Change SE driver name for t124Shravani Dingari
Bug 1271895 Change-Id: Ifaa409d5eba78659c9be5c3348d21d0a0e2c0ebe Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/222902 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-14crypto: tegra-se: Fix clock and queue issues on FPGAShravani Dingari
Changes required for T124 FPGA platform to run SE tests Bug 1206795 Change-Id: I91d142c5330714e0899d8e45d8caa876cc8fb0a7 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/191986 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
2013-09-14crypto: tegra-se: Use proper rsa key slotvenkatajagadish
This change fixes the S.E time out errors while executing RSA test Bug 1218410 Change-Id: Icbbcdd7b3d86a259dc3ff19ebb4b3a7374135e47 Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/199260 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14arm: tegra: Modify MC domain APIsPrashant Gaikwad
Change Tegra MC domain APIs used to add device and subdomain to use device and domain name instead of MC clock domain references. Using references creates dependencies on domain instances and future chips has different clients for domains. Bug 1010971 Bug 1276897 Change-Id: I08b9e2c506b7fa8b307663578ca413ffd63b9851 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/221997 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14crypto: tegra-se: Enable ROs, entropy clock for DRBGShravani Dingari
Enable Ring Oscillators for DRBG during SE initialization and also entropy clock required for the ENTROPY source Bug 1194672, Bug 1250871 Change-Id: Id29be0f0525fa5cc037f52fb76442f4d443fb76e Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/211597 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-09-14crypto: tegra-se: Change SE DRBG settingsShravani Dingari
Change in encryption mode, reseed interval and RNG source according to the RNG characterization done Bug 1058470 Change-Id: Ib2f095315a87424ea7989d89b9e73892957aed37 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/206270 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14crypto: tegra-se: put device into runtime suspend state when suspendingEric Miao
To prevent the device being accidentally put into runtime suspend state during the whole system suspend process, pm_runtime_get_noresume() is called upon _every_ device to increase the usage count (please refer to drivers/base/power/main.c). Since we don't explicitly disable the clock, pm_runtime_put_sync() in each operation in tegra_se_suspend() will not actually call the runtime suspend function, thus leaving the clock still enabled. To fix this issue in a simple way, we call pm_runtime_put_sync() in the end of tegra_se_suspend() to decrease the usage count to "0" and thus call tegra_se_runtime_suspend() in turn to disable the clock. To pair the usage count, we do a pm_runtime_get_noresume() in tegra_se_resume() as we don't actually need to runtime resume the device there. Bug 1246029 Change-Id: I64520b022b896f2867934255a55b852fafac4b63 Signed-off-by: Eric Miao <emiao@nvidia.com> Reviewed-on: http://git-master/r/206658 (cherry picked from commit 762c897f0ccd4bf3282cd8f97c869b07f3feba45) Reviewed-on: http://git-master/r/214949 Reviewed-by: Hunk Lin <hulin@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14crypto: tegra-se: Don't enable ROs in SE resumeShravani Dingari
Enabling ROs is taking time and during this time if entropy is used, S.E hangs. Hence disabling ROs in resume. Bug 1249497 Change-Id: I961b3e317490658142b19fc2af3177f80edcf6ec Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/207557 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2013-09-14crypto: tegra-se: Enable RO entropy source for DRBGShravani Dingari
Bug 1194672 , Bug 1213276 Change-Id: I2a1d033b5da8782b802f9dbac0461a596942b968 Signed-off-by: Shravani Dingari <shravanid@nvidia.com> Reviewed-on: http://git-master/r/204402 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14ARM: Tegra: Add devices to MC clock domainPrashant Gaikwad
Add devices to monitor for MC clock to the domain. MC clock domain will be turned off when these devices are runtime suspended. Bug 1010971 Change-Id: Ica4f9fbbd2cc8f52422a787b45cfae37bc60e130 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/204945 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2013-09-14crypto: remove reference to privare nvmap.hKrishna Reddy
Prepare for marshal/unmarshal of nvmap handles. Bug 1228120 Change-Id: Iac40a50cb96e39ce21929534f2df6b751eedb6cf Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/203026 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jon Mayo <jmayo@nvidia.com> GVS: Gerrit_Virtual_Submit
2013-09-14gcov-kernel: Add GCOV_KERNEL := y to MakefilesJuha Tukkinen
These changes have no effect if CONFIG_GCOV_KERNEL is not set in defconfig. It is easier to trigger GCOV for kernel if this patch is in by only setting the before mentioned flag. Change-Id: I8aade309da2da62c4b3889bd84e4123ba8f182da Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/62999 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R4c238f707f1db600f188ae83426336753992b7be
2013-09-14crypto :tegra-se : use dma_sync_* API's in tegra-sevenkatajagadish
using dma_sync_* API's in tegra-se driver will ensure memory coherency Bug 984024 Change-Id: I4b71c4a6a920ba3b933eac1fa500288508056b92 Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/174105 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-09-14crypto: tegra-se: change SE freq based on algoMallikarjun Kasoju
change S.E frequency based on the algorithm being used Bug 1014636 Change-Id: I49d1d15d0da0a9c76c3eda7d86872678dfe8d911 Signed-off-by: Venkatajagadish <vjagadish@nvidia.com> Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/132551 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
2013-09-14crypto: tegra-se: Remove unused codeSri Krishna chowdary
coverity id: 20917 Bug 1046331 Change-Id: Ia5653fff5df8cb0b5d8bda838b8d7cd883527fa0 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/167944 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2013-09-14crypto: tegra-se: Remove key slot index for DRBGvenkatajagadish
This change removes T114 SW war for DRBG key slot index. Bug 1033121 Change-Id: If44cb707158acc1becea5da9e933fb2eb7e86df4 Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/165628 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
2013-09-14crypto: tegra-se: Remove reseed rng T114 SW WARvenkatajagadish
This change removes T114 SW war to reseed the rng after RESEED_INTERVAL. Bug 1002118 Change-Id: I4f504349dd4a9a89d77b373808d82b41b3fcf736 Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/165614 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14crypto: tegra-se: Remove T114 Sw War to Limit max bytesvenkatajagadish
Remove the T114 S.E SW War to limit the Max bytes to process . Bug 961707 Change-Id: I16bcc36d0a1f1449b015bc3084634a34aaf30f4e Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/165613 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14crypto: tegra-se: Remove NOP after context savevenkatajagadish
Remove NOP command after lp0 context save fot t148. Bug 1002132 Change-Id: I2af181b02ff3ba64a60f2ad325fefee49e69c023 Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/165612 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
2013-09-14crypto: tegra-se: to_phys(ctx_save_buf) in PMC scratch registerHiroshi Doyu
Find physical address of ctx_save_buf via vmalloc_to_page(), and set it in PMC scratch register. Bug 1162056 Change-Id: I8ab16fd1381954883f3b51a30e958b1f343dd4e8 Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/165732 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
2013-09-14crypto: tegra-se: add chained scatter list supportvenkatajagadish
This change adds chained scatter list traversing support to S.E. Driver. Bug 1010604 Change-Id: If4073b7cf9c8ac901b8d0bd21ddc035e1e6b7ffd Signed-off-by: venkatajagadish <vjagadish@nvidia.com> Reviewed-on: http://git-master/r/147890 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com> Rebase-Id: Rbc765d613acf0c1dfcf0bbc10bcdde1ed602149a
2013-09-14crypto: tegra-se: Fix t114 SE context save failureMallikarjun Kasoju
t114 has sticky bits for RSA key slots which is not there in t30. Context save buffer offsets are adjusted appropriately for this. Change-Id: Ifd4e59772a869358d8dd12262e882fa63c53f054 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/159890 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: R39b4f1e4608ae52b3ab499c0df9472797d9b0c50
2013-09-14crypto: tegra-se: add NULL checkSri Krishna chowdary
Fix coverity issue by adding null check before pointer dereference. Bug 1046331 Change-Id: Ib4087056f5fb4c1d48f522c43065cd49a0ea5253 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/159498 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Re65dcfcdf52d2292a5c85011dde6ab3607bbb63a
2013-09-14crypto: tegra-se: moving to clk prepare APIsSivaram Nair
The clk_enable/clk_disable pair of APIs are replaced with clk_prepare_enable and clk_disable_unprepare. This is needed for the migration to common clk framework. Bug 920915 Change-Id: I697d80e857a040e97ea56adee104ae990419c5b6 Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/146796 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com> Rebase-Id: Rba75017aadc77b1b9519b32b5e1e9e37e9d7d2c0
2013-09-14crypto: tegra-se: issue NOP after context saveMallikarjun Kasoju
Issue NOP command after lp0 context save so that RSA can be performed if any. Bug 946811 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/132652 (cherry picked from commit d28ee9a7c6e2ad426f373a86b12b845422dd28c1) Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Change-Id: I77f2c5f71dac44ed89e638dc23dc6abcb844400d Reviewed-on: http://git-master/r/146654 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: Ra19f263610c3688c1c9c3ab41d7976d5d2af9224
2013-09-14crypto: tegra-se: LP context save support for t11xMallikarjun Kasoju
Add Security Engine low power context save support for t11x Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/132651 (cherry picked from commit 935b99c49bc593af6cfd709d0a2b5c8784cb0e6e) Change-Id: I6464a4dd42c0dc22ecab2ac9e358abb7e19acb70 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/146514 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Rebase-Id: R702e42e18cce95db84d849cdf1a768ac6ded32f8
2013-09-14crypto: tegra-se: fix coverity issueSri Krishna chowdary
Dereference after NULL check. Bug 1046331 Change-Id: I9438cf4aba92bec2c0aaccb5e272368a1bd99693 Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/142204 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: R8fa356e278ce778b847508d31d96e8a334cf106d
2013-09-14crypto: tegra-se: fix coverity issueSri Krishna chowdary
Add assignment after NULL check. Bug 1046331 Change-Id: Ib82f18b3119fb3333ce57494e854cdbc557f1acc Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/133520 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: R58e9be503f91761fd24cea6683edf3ab8265649f
2013-09-14crypto: tegra-se: reseed rng after RESEED_INTERVALMallikarjun Kasoju
Force ressed rng number generation after reseed interval expires Bug 952135 Change-Id: I3259b7ce008769c736e9b548a78494501acab60f Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/130994 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Rebase-Id: Rab560ce2a2ae9637020e4d9ac279d2b9c86e0b3b
2013-09-14crypto: tegra-se: Limit max bytes to processMallikarjun Kasoju
Security Engine can process maximum of 0xFFFFF 16 byte blocks. Add check condition for the same. Bug 961700 Change-Id: Iade1abfd27a9b784de8e0a59f319d403a4beb187 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/123291 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com> Reviewed-by: Venkat Moganty <vmoganty@nvidia.com> Rebase-Id: R5f63f4f627e2b5f73f45c0bf565e933a9484d374
2013-09-14crypto: tegra-aes: remove unused variableStefan Becker
Bug 1024089 Change-Id: I185016635729d3e1fb853a680ca6e66f7fc3c714 Signed-off-by: Stefan Becker <stefanb@nvidia.com> Reviewed-on: http://git-master/r/122363 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-by: Oskari Jaaskelainen <oskarij@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Frank Bourgeois <fbourgeois@nvidia.com> Rebase-Id: R88c5323090580428e2b7eed221d45c6b9be534d1
2013-09-14crypto: tegra: treat compilation warning as errorschowdary
- Add compilation flag to treat warning as error bug 949219 Change-Id: Ie5b8eb8ebb3ca37ac111fb0acc64cd8667e2c8e1 Signed-off-by: schowdary <schowdary@nvidia.com> Reviewed-on: http://git-master/r/118079 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Rebase-Id: R36746cc607e824cbdc2df561c741be98cf936577
2013-09-14crypto: tegra-se: Program slot zero for RNG operationMallikarjun Kasoju
RNG operation updates UIV. So program reserved slot i.e., slot zero before every RNG operation. Bug 1017413 Change-Id: I831b8cfd275ebecb5e6df3166a977b0cc5a26a8a Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/115992 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com> Rebase-Id: R975dfdbe2e66aaa5351ddc0bff39a95ec663d5d0
2013-09-14crypto: tegra-se: Enable interrupts after clock enableVictor(Weiguo) Pan
Because SE interrupts could be enabled in bootloader, if it's not cleared before jumping into kernel, it continues to assert the interrupt line to interrupt controller. When SE interrupts is enabled in kernel, to access SE registers in IST without clock enabled hung the CPU. To fix this issue, interrupt enabling is moved after clock is enabled. bug 1010334 Change-Id: I1b909efce2c9d92c3112039fc217f7c1360f9bbb Reviewed-on: http://git-master/r/113073 (cherry picked from commit b06e6662f738ad01a3b2b6803db654abaa03385e) Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com> Change-Id: Ide4b0295c781e0bba7aa071616e3e6160e44ee76 Reviewed-on: http://git-master/r/114064 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R1305d95edece3af1653a8e8ad5e86dc5aded76f4
2013-09-14crypto: tegra-aes: synchronize dma buffer accessSanjay Singh Rawat
- Using the dma sync apis to keep coherency. bug 984039 Change-Id: I9e389d2679f05c519ae4a51462247b7efeae01ca Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/111612 Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com> Rebase-Id: R738467b1b48a08e33c11deccabb35d5d20a2ac29
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 16:26:04 +0000