Age | Commit message (Collapse) | Author |
|
The instruction sequency "dsb sy" followed by "isb" functions as
a speculation barrier, which prevents the instructions after that
from being speculatively executed.
bug 2039126
Change-Id: Ie3b7b873a12002617e60510ed8759bdaa7cd7057
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618222
Signed-off-by: James Huang <jamehuang@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1650093
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
(cherry picked from commit f125c60045878513902cac4a084fde9a516eb3e2)
Reviewed-on: https://git-master.nvidia.com/r/1660782
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
|
|
This reverts commit 584b60200b8bdcc895c8edacb94f48db5929f70a.
Change-Id: Ibe5b217521b77fa5799400b9460182e3329e1779
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/1216501
(cherry picked from commit 04c8d66d61e15198b95d54672b2f2fe047d180b3)
Reviewed-on: http://git-master/r/1223596
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
|
|
enable shared memory config
Bug 1632724
Change-Id: I629eaa63ea54063dc713e21a848768378b3354a3
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/774295
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
|
|
This allows perform L1 cache clean alone.
Bug 200077334
Change-Id: I776de6e6726862e330b626fd19f8ae8f70055538
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/742254
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
|
|
Currently Android sync framework is used only in Android side,
however, it provides a generic synchronization framework that
can be used also in Linux.
This patch enables Android Sync framework on T124, T132 and T210
on Linux.
Bug 1601262
Change-Id: I46530a9b1b2245c0ddf8f7bc52b28af247350e14
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: http://git-master/r/677655
(cherry picked from commit 5998cc1d0d861986e34a74787650a79f3b1cd999)
Reviewed-on: http://git-master/r/714740
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
|
|
Change Tegra132 Jetson Model to jetson_t132
Bug 1569387
Change-Id: I67e97f821306b802aaaa475efc690c08926be556
Signed-off-by: Mike Thompson <mikthompson@nvidia.com>
Reviewed-on: http://git-master/r/562627
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
|
|
Enable Tegra Profiler for L4T.
Bug 1540280
Change-Id: I13f22d512c1e42d4ad91c03ed7825a8bdbbf2e93
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/450456
(cherry picked from commit 395d3b5d3fad1ac49b06d3b78004cbfce660c504)
Reviewed-on: http://git-master/r/481969
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Andrey Trachenko <atrachenko@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
|
|
Enable bluetooth core driver, protocols and HCI BT USB
driver support for t124 and t132.
Bug 200014428
Change-Id: Icd06f0326a75481a93d9805cbec1cfcd28c1131d
Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440501
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
|
|
get_user() should be called only for user_mode undef instruction.
Bug 1536343
Change-Id: Ia654783de0cf72abac6847ac9630236f9f0d6ebb
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/441348
(cherry picked from commit 518317f3e09c794e14de49f1afe47a93f92787ab)
Reviewed-on: http://git-master/r/448179
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
|
|
Add dtb support for t132 pm375.
bug 1522642
Change-Id: If0f769bceaf6edcd8fe5d2fbd067a2ed3a81cca2
Signed-off-by: Zheng Liu <zhliu@nvidia.com>
Reviewed-on: http://git-master/r/440519
GVS: Gerrit_Virtual_Submit
Tested-by: Mike Thompson <mikthompson@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
|
|
During boot, the CPU governor is getting set
to performance for a faster boot up and hence this
needs to be enabled.
Bug 1532473
Bug 1519610
Change-Id: Idf9ba9d30be1e09d9b9fc4245b96a43a56f2d799
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/436578
(cherry-picked from commit 876a19a97f0d85d270bef970a3815c039b4631fe)
Reviewed-on: http://git-master/r/437978
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
|
|
Previously, sysedp was attempted to enabled on non-battery versions of
P1761. This caused sysedp_batmon_calc to fail with -EFAULT during
probing as battery power supply was not available.
Bug 200018196
Change-Id: I0abb9cde8d597febed3e24d0bf3a29386e06db57
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/434985
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Rogers <srogers@nvidia.com>
Tested-by: Steve Rogers <srogers@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
We need to guarantee that our thread hasn't switched
cores between being asked to flush the local core's
tlb and having actually performed the task. If it
has, we need to perform a global tlbi.
Change-Id: I4b1bc5fbe53a7d35a2442753d8fe3f0ae86415ac
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/433805
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peng Du <pdu@nvidia.com>
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
|
|
Move cl-dvfs to DT for automatic voltage value
detection.
Bug 200017706
Change-Id: I3467c6e34648e6478b4929a47869ba71f0b251a0
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/434018
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
|
|
* Set NS bit when kernel is non-secure
* fix potential race in late_init
* enable hotplug notifier in late_init
* set buf occupied if immediately available
* better debugging print
Change-Id: I7acd736888f05facc559c7c965e20aea6f43060c
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/432822
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
|
|
Bug 1528672
Add monitor-data-new-workaround property
Change-Id: I930aa2df92a696834b68c76efd270e7b327024c9
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/429409
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
|
|
change invensens build method from dynamic library to
static library
- modify CONFIG_INV_MPU, CONFIG_INV_AKM8975, CONFIG_INV_BMP180
to be "=y", build those module as static library
- remove "insmod inv-mpu.ko", "insmod inv-ak8975.ko"
"insmod inv-bmp180.ko" command from init script
- set init priority of akm89xx/bmp180 as late_initcall
That will make sure system always loaded akm89xx/bmp180 after
inv-mpu module when those modules was builded as static library.
Bug 1468040
Change-Id: I0cf43f73b8654cadead45ed60c5f141e9197e111
Signed-off-by: Jajambo Liao <jajambol@nvidia.com>
Reviewed-on: http://git-master/r/424534
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
|
|
Change-Id: Ic7fa04925e34eda1cf1de28f599f85de53d14bfa
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/427122
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
|
|
Moved the LP0 error message that complains about CPU1 not being up on
LP0 entry (cpu_up failed) to a more appropriate location.
Bug 1522953
Change-Id: I9cfa7800779a621ca4563c6aefa7a7b2054ebe4b
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/427264
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peng Du <pdu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
|
|
- Fixed NULL pointer check before reference it.
- Also fixed some type cast warning message.
Bug 1517779
Change-Id: I8584017be83884f45e3f01a6fec60244440469c4
Signed-off-by: Yifei Wan <ywan@nvidia.com>
Reviewed-on: http://git-master/r/415443
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Peters <mpeters@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
|
|
Add the missing jump.
Change-Id: I85f7d9a89362529b6909fe56376e9ac9d8b4dfd2
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/345674
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/426713
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
|
|
Bug 1522953
Change-Id: Icb7fff057326a72a243037d3d64b88f99ac4fe68
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/422795
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
GVS: Gerrit_Virtual_Submit
|
|
Set the suspend_in_progress flag early in suspend_prepare and call
cpu_up on offline CPUs to get them out of C6 on suspend. This ensures
that all CPUs (CPU1) are in C7 before LP0 is requested.
Bug 1522953
Change-Id: I7f74f0afb2bfda92c03cc20262a6acaf8716d034
Signed-off-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/422815
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peng Du <pdu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
GVS: Gerrit_Virtual_Submit
|
|
Change-Id: Ifb524fe0a7061371136c380218fca8bc762b38ea
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/407169
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Eric Miao <emiao@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
|
|
Bug 200004840
Change-Id: I703d4843f8aab2ec63324f04cc13aaabae88e163
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/422174
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Conflicts:
arch/arm64/mm/proc.S
Bug 200004840
Change-Id: I76e0067839c96e3082b42c80d3fc670cf3d371b5
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/422173
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Removing cpu_relaxed_read and cpu_relaxed_read_long macros from
processor.h, as these macros are defined in asm/relaxed.h.
bug 1440421
Change-Id: Ic766ac6e34eefe93f90349c088626a0fb277670c
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/400127
(cherry picked from commit 108bf0b30d72c52e33dd4fec71dd1ed5baf13ed2)
Reviewed-on: http://git-master/r/422214
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Defined a new header file relaxed.h, which contains
arm64 specific macros which will be used to improve
power efficiency of arm64.
bug 1440421
Change-Id: Iee14115490cb16001d5eac9e309ee6e088b88f44
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/398323
(cherry picked from commit beb69cd6d2893c36712d4f927e41da0de729d651)
Reviewed-on: http://git-master/r/422212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
Defining relaxed version of atomic read as cpu_relaxed_read_atomic
which will be used for improving power efficiency for arm64.
bug 1440421
Change-Id: I5a88b8e66ec3021335905109010efc856ffa7c7e
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
(cherry picked from commit f53c05073d148adfe7abe153f1569c4bd655fb44)
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/415639
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
This commit adapts ab9d93ee40c641a502e834edda6223f45d8e2083
to ARM64
Bug 200012659
Change-Id: I34877c0c4a3863dbd2f7667958ff505362950a5e
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/422842
GVS: Gerrit_Virtual_Submit
|
|
Bug 1442659
Change retention voltage to .55V for PM374
Change-Id: I35fb398f738a91b2998c546699b1227ca5b24e42
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/420821
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Bug 1442659
Change retention voltage to .55V for P1761/P1765
Change-Id: Ica3947771a0379ec2177dc8cf819527629f19c5c
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/420227
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Bug 1442659
Change retention voltage to .55V
Change-Id: I22ae547fa3adb0213069693967a6176d7a628a09
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/420225
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Bug 1442659
Change retention voltage to .55V
Change-Id: I72a363e4898bf84f43afc16c56bf764c87d7b006
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/420224
Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
This should help debug bugs that show hard lock-ups.
Bug 200011588
Change-Id: Ib95b0b9be952151c7cc1889c867a4be54cda33f5
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/421448
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
|
|
into promotion_build
Change-Id: I9418a05ad5c56b2e902249218bac2fa594d99f56
|
|
Bug 1521482
Change-Id: I1d6756347e35030187a7f2fa61d7128c86ab94a6
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/412103
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
|
|
Currently core file of aarch32 process prstatus note has empty
registers set. As result aarch32 core files create by V8 kernel are
not very useful.
It happens because compat_gpr_get and compat_gpr_set functions can
copy registers values to/from either kbuf or ubuf. ELF core file
collection function fill_thread_core_info calls compat_gpr_get
with kbuf set and ubuf set to 0. But current compat_gpr_get and
compat_gpr_set function handle copy to/from only ubuf case.
Fix is to handle kbuf and ubuf as two separate cases in similar
way as other functions like user_regset_copyout, user_regset_copyin do.
Change-Id: If648f024eccfd96051646a04d799f94bd202bbea
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-on: http://git-master/r/419668
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
|
|
If a thread is compat, then stack start address is stored in
compat_sp not sp of pt_regs.
Bug 200006667
Change-Id: I4814d4b2a39224e0541ce988f84e038bca7d57bf
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/419378
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
|
|
This far the device has been powered off in non-atomic context.
This caused unexpected results when the kernel pre-empted the
power off sequence and started running some completely unrelated
task at the very same time. In addition, IRQs were enabled all
time allowing spontaneous interruption of the power off sequence.
This patch modifies the power off to happen in atomic context.
Original author for same change http://git-master/r/#/c/329636/
done for ARM kernel is Arto Merilainen <amerilainen@nvidia.com>
Bug 200007891
Change-Id: I9dfd5523ed838e3c181ef94dcbbb15e3b66419d1
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/418215
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
|
|
Bug 200004122
Conflicts:
drivers/cpufreq/cpufreq.c
drivers/regulator/core.c
sound/soc/codecs/max98090.c
Change-Id: I9418a05ad5c56b2e902249218bac2fa594d99f56
Signed-off-by: Ishan Mittal <imittal@nvidia.com>
|
|
Bug 1470221
Change-Id: I3e54e0eb3ab8d34c78905f6c4be71fd18a679628
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/415469
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Bug 1470221
Change-Id: I5cfdaa67faf784388f3456a6f5f58396485bb7ea
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/416795
Reviewed-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Tested-by: Karthik Ramakrishnan <karthikr@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chao Xu <cxu@nvidia.com>
|
|
Bug 1470221
Change-Id: Iadf57970008d7e3632cf2ec8b20952f75b42aa23
Signed-off-by: Hridya <hvalsaraju@nvidia.com>
Reviewed-on: http://git-master/r/417230
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
|
|
Compile wifi drivers part of kernel
Bug 1467982
Bug 1438249
Change-Id: If0960d496984be81d963d6bc35b145606fe54b5a
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/417118
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
|
|
The memory block for relocating lp0 vector is referenced by
a physical address (i.e. tegra_lp0_vec_start) which kmemleak
can't detect. Mark it as not a leak to avoid false positive.
Bug 200007297
Change-Id: Ie137f08d77911677d9e76fdb7d0112a1610dd72d
Signed-off-by: Allen Yu <alleny@nvidia.com>
Reviewed-on: http://git-master/r/415032
(cherry picked from commit 60520279ce2d6081a87a1bc1127046223b3839f6)
Reviewed-on: http://git-master/r/416824
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
|
|
Bug 1512428
Change-Id: Ic9541339b8d6113fe929bc2f7619bce9adce6c97
Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com>
Reviewed-on: http://git-master/r/411674
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
|
|
BUG 1512081
Change-Id: I7dab6d53f602b4e991c4165ad82e2e31a680a543
Signed-off-by: Megha Dey <mdey@nvidia.com>
Reviewed-on: http://git-master/r/413441
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
|
|
update emc dvfs table for P1761
Bug 1446755
Change-Id: I9895fad35e3861810f6511d9bb7b95b0fe6cfb70
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: http://git-master/r/415057
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
|
|
* fix flowctrl programming and apply for both cores
* go through cpu_resume to restore states for core1
Bug 1509408
Bug 1481103
Bug 1518263
Change-Id: Ie28ee2d2a081fdca8eef15c478c8a55644b4d846
Signed-off-by: Peng Du <pdu@nvidia.com>
Reviewed-on: http://git-master/r/412272
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
|