Age | Commit message (Collapse) | Author |
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This moves from a gpio to a pwm backlight driver to control
BKL1_ON and BKL1_PWM.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
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Add external clock nodes to model the on-module SATA reference
clock generator. Assign it to the SATA instance so it can be
disabled if required.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Add external reference clock via clock tree. This allows to model
the shared reference clock provided via PCIE_SATA_REFCLK100M_P/N
properly.
This is analogous to what we did for PCIe in commit db22e7590338
("PCI: imx6: add external clock support for i.MX8QM").
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Remove lpcg_xxx clocks (pcie_per) also in module level device tree.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Remove the lpcg_xxx clocks codes, since they are HW gated.
These clocks controlled by HW, and would be turned on
automatically, if there are access operations.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
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This reverts commit cd8afb78947d0a0c2fbe13935b261a835b26a86a.
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This reverts commit 91165e6fe1c95e7786385cafed9897ef9c7803c1.
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This reverts commit 6be9d4ba6f9e4bbb27b2ae4ba5be949183cab8bd.
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This commit adds code that forces setting the requested format in the
actual sensor driver.
Note that currently it is commented out as imx8 isi does not seem to
work properly with any other source resolution than the default
1920x1080.
Without this code, the driver will work with other resolutions (the ones
which are reported as supported by the connected sensors and lower than
1920x1080), but the image will be scaled down from 1920x1080. Scaling up
is not supported.
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The issue is that once the scaling was enabled, then the stream was
disabled and enabled again with a resolution that does not need scaling,
the actual scaling was never disabled in the ISI block. This made ISI
stream the scaled down with a large black padding.
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Make the get_src_fmt callback treat all yuv formats equally. This is
needed to recognize the actual source format as yuv and enable yuv->rgb
conversion in the image processing unit of iMX8.
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Until now, the device searched for the subdev (sensor dev) using the
device name. That was a hack and required a hard-coded name of the
device in the common code.
This commit fixes it and makes it look for the proper subdevice using
the media pads layer.
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Sensor ID counter starts from 0 while the actual device number starts
from 1. Fix the issue that it caused.
Without this fix it is impossible to make proper media pads connections.
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This commit makes the camera instantiation use the proper driver and
fixes all the settings so it works with Apalis.
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This driver is a copy of a driver by nVidia. It was improved by Antmicro
for the TK1 board.
Additionally there are some changes which were required to make it
compatible with iMX8.
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LVDS is treated as primary display by the kernel. So when both is
enabled, HDMI and LVDS, then LVDS is the primary display. Hence
demos using only one screen usually do not show anything on HDMI.
Since HDMI is used more often, and most customers probably do not
have a matching LVDS display at hand, disable LVDS by default for
now.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add NXP SGTL5000 codec support for Apalis iMX8.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add SAI1 I2S peripheral and SGTL5000 audio codec support for
on-module audio support. Note that clocking is currently setup
in the SGTL5000 codec node, altough it seems that due to cross
dependencies those clocks (or root clocks thereof) might get
changed later on. With the current clock frequencies audio
seems to play at the correct rate.
The power rails need further refinement.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add carrier board RTC support.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add DS1307 family RTC support which also supports M41T0 RTC as used
on our carrier board.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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The m41t0 variant is very similar to the already supported m41t00
variant, with the notable exception of the oscillator fail bit.
The data sheet notes:
If the oscillator fail (OF) bit is internally set to a '1,' this
indicates that the oscillator has either stopped, or was stopped
for some period of time and can be used to judge the validity of
the clock and date data.
The bit will get cleared with a regular write of the system time,
so no changes are needed to clear it.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
(cherry picked from commit 8566f70c8a90f3914b06e934852596ba94aaa381)
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Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add RTS/CTS signal to UART2. Also remove the wrong pins muxed
for UART3 (lpuart0). UART3 does not have RTS/CTS pins in the
Apalis standard.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Make sure USBH_EN is enabled by default.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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When pciea fails to probe, it disables X2 peripheral clock. When
pcieb probes subsequently, the kernel crashes with a "Unhandled
fault: synchronous external abort" in regmap_mmio_read32le.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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When the second controller initializes PCIe while the first failed
to initialize, the X2 peripheral clock will be off. This leads to
the following crash:
OF: PCI: host bridge /pcie@0x5f010000 ranges:
OF: PCI: No bus range found for /pcie@0x5f010000, using [bus 00-ff]
OF: PCI: IO 0x7ff80000..0x7ff8ffff -> 0x00000000
OF: PCI: MEM 0x70000000..0x7fefffff -> 0x70000000
Unhandled fault: synchronous external abort (0x96000210) at 0xffff00000e5b0008
Internal error: : 96000210 [#1] PREEMPT SMP
Modules linked in:
CPU: 2 PID: 1212 Comm: kworker/2:1 Not tainted 4.9.51-imx_4.9.51_8qm_beta2_toradex-06824-ga0b0515b3992-dirty #68
Hardware name: Toradex Apalis iMX8QM (DT)
Workqueue: events deferred_probe_work_func
task: ffff8008786a8000 task.stack: ffff800878e88000
PC is at regmap_mmio_read32le+0x8/0x18
LR is at regmap_mmio_read+0x40/0x68
pc : [<ffff000008629870>] lr : [<ffff000008629968>] pstate: 000001c5
sp : ffff800878e8b9a0
x29: ffff800878e8b9a0 x28: 0000000000000000
x27: ffff800878e8bba0 x26: ffff8008793ab700
x25: 0000000000000000 x24: 0000000000000000
x23: 0000000000200000 x22: ffff800878e8ba5c
x21: ffff800878e8ba5c x20: 00000000000b0008
x19: ffff8008793abc80 x18: 0000000000000001
x17: 00000000dbe14aa8 x16: 0000000069551cdf
x15: ffffffffffffffff x14: ffff800879342f04
x13: ffff800879342f03 x12: 0000000000000038
x11: 0101010101010101 x10: 0000000000000040
x9 : ffff00000921e600 x8 : ffff80087651c000
x7 : ffff80087651c028 x6 : 0000000000000000
x5 : 0000000000000000 x4 : 0000000000000000
x3 : ffff000008629928 x2 : ffff000008629868
x1 : 00000000000b0008 x0 : ffff00000e5b0008
Process kworker/2:1 (pid: 1212, stack limit = 0xffff800878e88020)
Stack: (0xffff800878e8b9a0 to 0xffff800878e8c000)
...
[<ffff000008629870>] regmap_mmio_read32le+0x8/0x18
[<ffff00000862208c>] _regmap_bus_reg_read+0x14/0x20
[<ffff000008623988>] _regmap_read+0x60/0xe0
[<ffff000008623d6c>] _regmap_update_bits+0x9c/0xd8
[<ffff000008624d78>] regmap_update_bits_base+0x60/0x90
[<ffff0000084633dc>] imx6_pcie_assert_core_reset+0x184/0x338
[<ffff000008465ce4>] imx6_pcie_host_init+0x34/0x2c0
[<ffff000008462bf8>] dw_pcie_host_init+0x230/0x518
[<ffff000008464ea4>] imx6_pcie_probe+0x49c/0x970
[<ffff000008609fe0>] platform_drv_probe+0x58/0xb8
[<ffff000008608304>] driver_probe_device+0x1cc/0x2c0
[<ffff000008608550>] __device_attach_driver+0x98/0xf0
[<ffff000008606508>] bus_for_each_drv+0x48/0x98
[<ffff000008608018>] __device_attach+0xc0/0x130
[<ffff000008608600>] device_initial_probe+0x10/0x18
[<ffff000008607580>] bus_probe_device+0x90/0x98
[<ffff000008607a1c>] deferred_probe_work_func+0x7c/0xb8
[<ffff0000080d3dac>] process_one_work+0x1d4/0x370
[<ffff0000080d3f8c>] worker_thread+0x44/0x4a8
[<ffff0000080d9e68>] kthread+0xf8/0x100
[<ffff000008082e80>] ret_from_fork+0x10/0x50
Code: d65f03c0 d503201f f9400000 8b214000 (b9400000)
Make sure that the peripheral clock is enabled right from start
before any register access.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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When pciea fails to probe, it disables X2 peripheral clock. Then
when pcieb probes, the kernel crashes with various errors, but
most often with a "Unhandled fault: synchronous external abort" in
regmap_mmio_read32le.
In contrast, X1 peripheral clock seems not to be required... Use
just X2 on both PCIe instances.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Make sure that the clock enable pin is assigned to the GPIO
clock driver.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Now that the HDP driver support HDMI CTRL GPIOs make use of it
and reference the HDMI_CTRL GPIO.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add support to control HDMI levels using a GPIO. The driver simply
sets the GPIO high for HDMI and low for DisplayPort.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add Marvell/USB Bluetooth support.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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With newer U-Boot the proper HDMI firmware gets loaded, with that
Linux can use the HDMI driver.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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With that external USBH2/3 do work now. Also the on-module
Azurewave AW-CM276NF Wi-Fi/Bluetooth enumerates after downloading
the firmware over PCIe.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Since beta2 the kernel crashes when trying to use HDMI I2C:
[ 0.793055] usbphynop2 supply vcc not found, using dummy regulator
[ 0.799867] i2c i2c-0: LPI2C adapter registered
[ 0.804437] i2c i2c-1: LPI2C adapter registered
<freeze>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Enabled new nodes crucial for graphics.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add Marvell Wi-Fi support using the mwifiex driver.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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The Apalis iMX8 does not make use of the PCIE_CTRL0_PERST_B signal.
However, the Apalis Evaluation Board uses GPIO7 as a PCIe reset
signal for the PLX PCIe switch. With this the Apalis PCIe port
comes up as Gen2 successfully on the Apalis Evaluation board.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add external clock nodes to model the on-module PCIe reference
clock generator. Assign it to the two PCIe instances so any of
those can be disabled if required.
Also add Wi-Fi pins to the PCIe B instance. The AzureWave
AW-CM276NF Wi-Fi/Bluetooth chip (using Marvell 88W8997 chipset)
appears on the PCIe bus:
00:00.0 PCI bridge: Freescale Semiconductor Inc Device 0000 (rev 01)
01:00.0 Ethernet controller: Marvell Technology Group Ltd. Device 2b42 (rev 11)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add external reference clock via clock tree. This allows to model
the shared reference clock provided via PCIE_SATA_REFCLK100M_P/N
properly.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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HDMI is currently not working, disable for now. This prevents the
X-Server does not spawn accross HDMI/LVDS output by default.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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With a valid master clock and power down/reset GPIO correctly
specified the sensor is detectable via I2C. However, the sensor
driver does not work with the i.MX8QM camera stack yet, further
investigations are needed.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add GPIO fan/backlight for Apalis iMX8. Enable USB camera support.
Also enable configs relevant for MIPI CSI2 camera (OV5640) support,
but this needs further changes to the driver to work with i.MX8QM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Currently the master clock is missing hence the camera can not
work. Further investigations are needed.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Add support for the on-module USB HSIC hub.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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When using a GPIO which is high by default, and initialize the
driver in USB Hub mode, initialization fails with:
[ 111.757794] usb3503 0-0008: SP_ILOCK failed (-5)
The reason seems to be that the chip is not properly reset.
Probe does initialize reset low, however some lines later the
code already set it back high, which is not long enouth.
Make sure reset is asserted for at least 100us by inserting a
delay after initializing the reset pin during probe.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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Use GPIO backlight driver and specify for BKL1_ON and BKL1_PWM
as a GPIO for now. There seem to be no driver for the LVDS PWM
currently.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
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