Age | Commit message (Collapse) | Author |
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program pwren signal of max8907c regulator to power down/up core rail on
deep sleep enter/exit deep sleep mode.
core_timer and core_off_timer changed as per K32.
separate_req set to false as whistler pmu has combined power requests.
Bug 817378
Change-Id: Ia95a61360079f919a039572cf8fd4597db9efd50
Reviewed-on: http://git-master/r/28435
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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apis added to program max8907c regulator to power down and up core supply rail
via the pwren signal on enter and exit deep sleep mode.
Bug 817378
Change-Id: I5af04db22b6c84fc4359c1a0cf209710ca144159
Reviewed-on: http://git-master/r/28434
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Conflicts:
arch/arm/mm/proc-v7.S
drivers/video/tegra/dc/dc.c
Change-Id: I40be0d615f14f1c01305388a706d257f624ba968
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Resolve potential race between resume and reset
Fix wmb after return
Change-Id: I98ad1e713b9781d780bf93561496011bf62b86d1
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
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Fix SSL3250A camera flash I2C errors.
Bug 778859
Change-Id: Ifaf800405bcfc080a66c500cb74fe87ca3074be9
Reviewed-on: http://git-master/r/28205
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug 787628
Change-Id: I73c3b8f0b3e69f1c4bc13bdaea84b19b14eb73d1
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/28003
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Rabin Vincent reports:
| On SMP, this BUG() in save_stack_trace_tsk() can be easily triggered
| from user space by reading /proc/$PID/stack, where $PID is any pid but
| the current process:
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| if (tsk != current) {
| #ifdef CONFIG_SMP
| /*
| * What guarantees do we have here that 'tsk'
| * is not running on another CPU?
| */
| BUG();
| #else
Fix this by replacing the BUG() with an entry to terminate the stack
trace, returning an empty trace - I'd rather not expose the dwarf
unwinder to a volatile stack of a running thread.
Change-Id: Ide38bb5eeff09c1d1189bc1a30667a2cc6b96ba2
Reported-by: Rabin Vincent <rabin@rab.in>
Tested-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-on: http://git-master/r/28325
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Change-Id: I5cdfdfef8dfc9ff4796e8a9b53d9af8f41e49e65
Reviewed-on: http://git-master/r/24360
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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- configured the pinmuxes needed by the baseband.
- added board specific baseband related code.
- added caif specific platform data needed by protocol layer.
bug 785523
Change-Id: I2d1936419ccd9190d6539836cb8bca563ea07c6e
Reviewed-on: http://git-master/r/23432
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
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Change-Id: I903db54b76781cdb9231bb25d79635cb8f264087
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To ensure an accurate read of the RTC registers during the required
multi-byte read operation, the PMU RTC is designed with the following
protection scheme
- A circuit detects a write/read and locks the RTC_COUNT4 value
by keeping the RTC in a suspended mode
- During the suspended mode, a secondary counter is used to
keep track of all counts that would have normally incremented the RTC
- After the read is complete, the value of the secondary counter is
added back to the RTC registers and thereby keeping the RTC accurate
- The backup counter allows for a 1ms RTC suspend mode duration
when the RTC prescaler is enabled.
i2c needs to generate a 2 msgs when reading.
- the address setup(write RTC_COUNT4 operation),
hence start locking the RTC_COUNT4
- the data transfer (read RTC_COUNT4 operation),release locking it.
this may allow the CPU to execute other portions of code
in between the two operation.
The fix is to start a PMU RTC access by reading the register prior to
the RTC_COUNT4 so that access of the RTC PMU registers will be guaranteed
to always occur within the 1ms time period.
- the address setup(write RTC_COUNT4-1 operation),
so there is no locking the RTC_COUNT4
- the data transfer (read RTC_COUNT4 operation),
starting locking the RTC_COUNT4 and release locking the RTC_COUNT4
in one operation, so it will be guaranteed within 1ms
Bug 811075
Change-Id: Ie07472a329f6a0eed11e6a039cd93307bb5276a0
Reviewed-on: http://git-master/r/27537
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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bug 811316
Change-Id: I4513f81719a60c8f214ee07082e58defb1cca0aa
Reviewed-on: http://git-master/r/26985
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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bug 816348
Change-Id: I6551a867fdfcddc6689d6fcc1daaee11d8879e7f
Reviewed-on: http://git-master/r/28182
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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there was a cropping code which saves from out of FB.However,
the cropping code was wrong and cropping should be done from
usermode driver instead of kernel. a warning is added here
for easy debugging
Bug 792524
Change-Id: Id57243e36f903b14a093dad23a6111032890c01a
Reviewed-on: http://git-master/r/28055
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Tested-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Fix SSL3250A camera flash I2C errors.
Bug 778859
Change-Id: I086eb863cce343a107f5f382d2b96eecf70d6902
Reviewed-on: http://git-master/r/28202
Reviewed-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Tested-by: Erik M Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 803932
Change-Id: Idfafba37e71e80bce1b70a7324daf5e8df2a9e0d
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28174
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 803932
Change-Id: I52703d6281bf613d7ccf67c38daf6412ac790c74
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28173
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 803932
Change-Id: I61cf41423d08d2f2c19f314269be9e8ee6255b9b
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/28172
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Removes the Sidetone enable code, sidetone should
not be enabled for normal capture.
For Bug: 808731
Change-Id: I7159c023624c9d3f759cf52510e8a48551454db1
Reviewed-on: http://git-master/r/28013
Tested-by: Manjula Gupta <magupta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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PPP handles packet loss but does not work with out of order packets.
This change performs reordering of incoming data packets within a
sliding window of one second. Since sequence number is optional,
receiving a packet without it will drop all queued packets.
Currently the logic is triggered by incoming packets, so queued
packets have to wait till another packet is arrived. It is done for
simplicity since no additional locks or threads are required. For
reliable protocols, a retransmission will kick it. For unreliable
protocols, queued packets just seem like packet loss. Time-critical
protocols might be broken, but they never work with queueing anyway.
Signed-off-by: Chia-chi Yeh <chiachi@android.com>
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Change-Id: I023482f230dc4f413647f47b3c7c36fd4c98b97d
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Prevents HDMI detect worker from re-disabling DC during
suspend (after tegra_dc_suspend has disabled DC itself)/
Change-Id: I90016fb709934ab8fb5135443980898069f8071f
Signed-off-by: Andrei Warkentin <andreiw@motorola.com>
Signed-off-by: Erik Gilling <konkers@android.com>
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When HDCP repeater has no device attached, DEVICE_COUNT reports back as 0.
HDCP driver should handle this case as a good case and continue downstream
authentication, other than fail it.
Change-Id: Ied2e46428c0247f14fbd96016cd4fdbf358f6587
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Change-Id: Ibf21f94d93ef237de6ab379dc1aa2498df08cdbd
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Add registration and initialization of soc380 camera
Bug: 783488
Change-Id: I9ad9d25cfa51a45b2fe889cdac5b90650eafdd03
Reviewed-on: http://git-master/r/24973
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Enabling soc380 front camera sensor.
Bug: 783488
Change-Id: I306cd91765cf0148fcd633e86667643d556b2f2d
Reviewed-on: http://git-master/r/24971
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug: 783488
Change-Id: I0d70ec5bb0fd880b167e9ced0e002829abeccdbf
Reviewed-on: http://git-master/r/24969
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug 783488
Change-Id: I25516842591f60304e7fdaa32717c96a313005ca
Reviewed-on: http://git-master/r/26974
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Bug 783488
Change-Id: I609ed3c7d87633af53244357bc630fc7de00073c
Reviewed-on: http://git-master/r/26973
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Add AD5820 focuser driver for Whistler.
Bug 783488
Change-Id: I0d8a08e7df9f472ffc4edfe7bfa255357bff5126
Reviewed-on: http://git-master/r/26970
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Register assignments were wrong for incoming overlay blend
parameters. DisplayManagerLite policy sets src combine mode
to premult to signal dst premult aplha blending. But the DC
expects premult set for the dst window for this mode.
Bug 796009
Change-Id: I5929bc4cd362ac60c7a9f14bb4ae83da04b857ab
Reviewed-on: http://git-master/r/26835
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Enable camera flash/torch
Bug 778859
Change-Id: I50fee49253cc03c583be96a972ae20f06d33d7ac
Reviewed-on: http://git-master/r/26915
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Add board level support for camera SSL3250A flash.
Bug 778859
Change-Id: I7375757546d7ed54dace9f9cd03adeee84959126
Reviewed-on: http://git-master/r/26903
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Change-Id: I30dfa03324eb5c4c344c62578eb808a150c80deb
Signed-off-by: Erik Gilling <konkers@android.com>
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Bug 771653
Change-Id: Idb3b901d208c22eaa50e670afb405b562e9936cb
Reviewed-on: http://git-master/r/27563
Reviewed-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Tested-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Reviewed-by: Maria Gutowski <mgutowski@nvidia.com>
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Change-Id: I318afbe66efa346b71e82413ac6442672cef4d36
Reviewed-on: http://git-master/r/21196
Reviewed-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Tested-by: Jonathan B White (Engrg-Mobile) <jwhite@nvidia.com>
Reviewed-by: Maria Gutowski <mgutowski@nvidia.com>
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Wait for CPUs to indicate that they've stopped, after sending the
stop IPI, rather than blindly continuing on and hoping that they've
stopped in time. Print a warning if we fail to stop the other CPUs.
Bug 810939
(cherry picked from commit 28e18293cf0f8d23a0950d7b1d2212d11af494dc)
Change-Id: I87fbaad50a50789dc9a12b1f27d51372ffd6aaf1
Reviewed-on: http://git-master/r/27828
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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use pixel clock to configure HDMI interface signaling properties.
These options are different depending on which SoC.
Bug 786961 Bug 795251
(cherry picked from commit a59e2483a9f85a72186f51c124709401af554eb3)
Change-Id: Ie5ef35fe03065d3e77831a0e1a2bbf8319d04125
Reviewed-on: http://git-master/r/27722
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Reviewed-by: Jessica Liao <jeliao@nvidia.com>
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-Removed unused sensor mode mode_1920x1088
-Added ov5650_write_reg_helper function to do write_reg()
according to camera_mode.
-ov5650_get_status function is removed as it is reading reg 2
value and there is not any definition of reg 2 in datasheet and
even user space is not using it's value at all.
-Added ov5650_set_power function to on/off camera sensors power
according to camera_mode.
-Added ioctl OV5650_IOCTL_SET_CAMERA_MODE to set camera_mode
from user space.
-Added i2c driver for right ov5650.
Bug 809921
Change-Id: Ib3cf43d0a064c18c218d0850e849fff84e18e661
Reviewed-on: http://git-master/r/26857
Tested-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: George Bauernschmidt <georgeb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 809921
Change-Id: I3de13b3e53471c2550284b41e52fc191bba87f8b
Reviewed-on: http://git-master/r/27033
Tested-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: George Bauernschmidt <georgeb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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nvmap's debugfs had a bad format so it was
very difficult to read the outputs. this commit
fixes it and added total allocation size along
with it
Bug 813891
Change-Id: I6e3165b3ff917d9510d39f1e35b8e6b59c086592
Reviewed-on: http://git-master/r/27349
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Tested-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This kernel driver will replace the functionality that was
previously in the NVRM daemon root process and allow multiple
instances of OpenMAX to function and AVP resource tracking and
cleanup.
Bug 772210
Change-Id: Ia5eb559cde4644bae5fd8b23a1de57cd65f3fdd8
Reviewed-on: http://git-master/r/25115
Tested-by: Stephen Holmes <sholmes@nvidia.com>
Reviewed-by: Stephen Holmes <sholmes@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- added the tegra dependent layer of the caif protocol.
- integrated with the open source rainbow caif.
- verified the functionality using latest rainbow RIL.
bug 785523
Change-Id: I75be8d2ef6e5562facf902a3f963f34d241bb6c3
Reviewed-on: http://git-master/r/23421
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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Specified OSC_SRC_SEL flag to force clock signal to be taken from
an externally generated source rather than be calculated internally.
This should raise the accuracy to within +/-2 seconds/24 hours.
Bug 811075
Bug 810537
Change-Id: I7b7c4e4d752fdc03b81239f362a1d6f7aa4d3b92
Reviewed-on: http://git-master/r/27222
Reviewed-by: Andre Sihera <asihera@nvidia.com>
Tested-by: Andre Sihera <asihera@nvidia.com>
Reviewed-by: David Schalig <dschalig@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
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Adding the support for mass storage feature.
Bug: 806260
Change-Id: I9a991b9056f838e6f59326975e6b7510ac41a155
Reviewed-on: http://git-master/r/27641
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
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Enabling the support for mass storage.
Bug 806260
Change-Id: Iea160814a9062e995c9d644df3e76f45eaba0fba
Reviewed-on: http://git-master/r/27643
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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