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2010-08-20[ARM/tegra] RM: Integrated EMC DLL process dependency.tegra-10.8.2Alex Frid
Implemented EMC digital DLL setting dependency on process variations and scaling frequency. Bug 722439 Change-Id: I558f2dfbfe09eb16010875f2ba8a1a963c95e50f Reviewed-on: http://git-master/r/5383 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-20[arm/tegra] ventana: Enabling CONFIG_SENSORS_LM90Laxman Dewangan
Enabling config variable CONFIG_SENSORS_LM90 for enabling temperature monitoring through ON semoconductor's NCT1008 temperature sensor. The NCT1008 is driver compatible with National semiconductor's LM90 temperature sensor. Change-Id: I263932fe283b75384acd36c486da20fbe9ec5efb Reviewed-on: http://git-master.nvidia.com/r/5079 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-19tegra: Save restore pad control registers acorss LP0Venkata (Muni) Anda
Pad control register should be saved before LP0 and restored after LP0. (cherry picked from commit df7e8107f49e15d5652b63b5a3d35121b9f722ad) Change-Id: I8679de6bccf6292a41a79b5603a9f02da41f8b15 Reviewed-on: http://git-master.nvidia.com/r/5333 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-19[arm/tegra] nct1008: Adding board info for temp sensor nct1008.Laxman Dewangan
Adding the board information for the device nct1008. This is ON semiconductor temperature sensor and driver compatible with national semicoductor LM90. The board info is getting register if config variable CONFIG_SENSORS_LM90 is selected through def config file. Change-Id: I2d49dec6ef0942823654b8f00cf62742f0136273 Reviewed-on: http://git-master.nvidia.com/r/5078 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-19[driver/hwmon] lm90: Adding nct1008 as supported list.Laxman Dewangan
The ON semiconductor's temperature sensor NCT1008 is driver compatible with National semicondutor's LM90 driver. Adding NCT1008 as the list of lm90 driver id table. Change-Id: I3dcbe1cdd1441e5196239551265444ebb633a1a2 Reviewed-on: http://git-master.nvidia.com/r/5080 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-19[ventana] DVFS table.Suresh Mangipudi
Integrate the DVFS table for ventana. Change-Id: I2be06e78893f544c1e180438d6650138b7973c1b Reviewed-on: http://git-master/r/5085 Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-19nvhost: Reimplement null kickoff functionality.Antoine Chauveau
For each channel submit where null kickoff is requested, we don't place the user's commands in the pushbuffer. All necessary context switches, syncpoint increments and waitbase increments do happen though. Bug 717235 Change-Id: I51c323729ea57993a5b52fb395ab90cb8608ee6b Reviewed-on: http://git-master/r/5091 Reviewed-by: Antoine Chauveau <achauveau@nvidia.com> Reviewed-by: Antti Hatala <ahatala@nvidia.com> Tested-by: Antti Hatala <ahatala@nvidia.com>
2010-08-18[ARM/tegra] RM: Re-arranged voltage request limits.Alex Frid
Re-arranged the order low corner limit is applied to voltage request to guarantee that no actual PMU transaction is triggered (= no clock control re-entry) if peripheral clock is disabled concurrently with low corner increase. Bug 717899 Change-Id: I854164998fa8e88651950fb5aeed3b8595c3c10b Reviewed-on: http://git-master.nvidia.com/r/3757 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-18[arm/tegra] spi: Fixing warning dump when timeout err happen.Laxman Dewangan
If transfer started and driver waits for transfer completes with given timeout, and if transfer have not completed in a given timeout then driver handles the erro_timeout case. In this error handling, it does not need to call the Interrupt done as it has not been interupted yet. Calling unnecessarily InterruptDone create warning for unbalanced call. Change-Id: Id7f924eefcd49131b9f752d530b108ab08874b57 (cherry picked from commit 31bc11d7583d089673cb0c474f210343a729e8da) Reviewed-on: http://git-master/r/4377 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-18tegra fuse: fixing fuse and AP compatibility issuesVenu Byravarasu
As Fuse ddk was not correctly storing SecBootDeviceConfig value, there was a mismatch between GfShell and Sysfs. These issues are fixed with this change. tested on: Whistler using GfShell and Sysfs Bug: 715134 Change-Id: Iccca2c1f9608f63938557b0ef0e88aff012bd574 Reviewed-on: http://git-master/r/4976 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-18tegra accelerometer: Changed default initialization parametersPritesh Raithatha
Re-enabled accelerometer for whistler. Fixes bug 721469 Fixes bug 704850 Change-Id: I5eb9b04092df11b82b3e43e6c9699b579945576f Reviewed-on: http://git-master/r/5278 Tested-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-17[ARM/tegra] odm: corrected the polarity of the baseband wakeup pin configurationSheshu Shenoy
Change-Id: I33c6abe2739f13eaf6dab2c98a910048f3733b85 Reviewed-on: http://git-master/r/5213 Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-17tegra accelerometer: power management changesVenu Byravarasu
Added suspend and resume functionality to tegra accelerometer, for supporting LP0 on Ventana tested on Ventana-C bug 716080 Change-Id: Ib57b3f2f0d3bec77839f40226f79cd60e222a366 Reviewed-on: http://git-master/r/4836 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-17[tegra/ventana] kernel config for bcm softapMichael Hsu
specify kernel nat / netfilter config options for wifi tethering Change-Id: I110f5246b6110f01455634e4f17138b388252103 Reviewed-on: http://git-master/r/5112 Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Rakesh Kumar <krakesh@nvidia.com> Tested-by: Rakesh Kumar <krakesh@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-17[arm/tegra] Serial: Confirming configured baudrate.Laxman Dewangan
Sometimes, in uart, the desired baudrate can not be configured in 5% error accuracy due to not finding the correct combination of clock source freq and integer divisor. In this case the driver should generate the error message. Change-Id: Iafe245876a2cb9810c1025c02a4b6a36eb26aa4c Reviewed-on: http://git-master/r/4974 Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-16tegra accelerometer: removing threshold settingVenu Byravarasu
As Threshold settings are done in a common place for different accelerometers, removing it. Need to add threshold settings to individual ODM driver based on the need. Bug 721469 Change-Id: I6fe20c4e501208dde9fcf47ac3e31bdf81343efc Reviewed-on: http://git-master/r/5082 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-16[ARM/tegra] timers: Updated timers on LP2 exit.Alex Frid
Moved hrtimer_peek_ahead_timers() call from LP3 entry to LP2 exit. The purpose of this call is to account for time spent in LP2. No need to do it on every LP3 entry. Also made sure that LP2 is entered only when scheduler tick is stopped. Bug 720021 (cherry picked from commit 44137c615f2942d37b18f51ab80356ec9dff9bbb) Change-Id: Ia63c3075778f2bc7ba465c386e80503b7c40a97f Reviewed-on: http://git-master.nvidia.com/r/5165 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: John David Moser <jmoser@nvidia.com> Tested-by: John David Moser <jmoser@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-16harmony odm: disable GPIO-PV2 as wake-up eventBharat Nihalani
gpio_pv2 is disabled as a wake-up source for Harmony, as it causes spurious interrupts when battery charging current is more than 120 mA fix for bug 717868 Change-Id: I9b42b81daac035b0ba3644e8b23a1c1d6a5f03bb Reviewed-on: http://git-master.nvidia.com/r/5140 Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-16nvhost: split hardware context state into refcounted objectAntti Hatala
Change-Id: I69bfed3522d7d2082530204d8f568458f2966638 Reviewed-on: http://git-master/r/5094 Reviewed-by: Andrew Howe <ahowe@nvidia.com> Reviewed-by: Antti Hatala <ahatala@nvidia.com> Tested-by: Antti Hatala <ahatala@nvidia.com>
2010-08-13[driver/mm_ak8975]: Adding suspend/resume functions.Laxman Dewangan
For the power managementi functionality for the device magnetometer ak8975, added the power suspend and resume functions. Change-Id: I40bc799d77dcbcc419200d9a6b6622415b520246 Reviewed-on: http://git-master/r/4790 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-10tegra sdhci: Prevent SDIO from suspend/resumePavan Kunapuli
To support wifi connectivity on system suspend resume for always powered on SDIO cards. Added card_always_on flag. This flag will prevent SDIO de-init/re-init in suspend/resume. If this flag is not set, then SDIO card is de-init/re-init on suspend/resume. Change-Id: Ib092fa9e0bc63ba781e0f4b6637dad0231303ba9 Reviewed-on: http://git-master.nvidia.com/r/4257 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Deepesh Subhash Gujarathi (Engrg-Mobile) <dgujarathi@nvidia.com> Tested-by: Deepesh Subhash Gujarathi (Engrg-Mobile) <dgujarathi@nvidia.com> Reviewed-by: Rahul Bansal <rbansal@nvidia.com> Tested-by: Rahul Bansal <rbansal@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Tested-by: Victor (Weiguo) Pan <wpan@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-10[ARM/tegra] clocks: Relaxed undefined tolerance.Alex Frid
Set min/max frequency request boundaries as "unspecified", if tolerance is not defined. Current code in such case requests exact frequency, which may not be reached with limited dividers granularity. This should fix 3D clock boost failure observed on Harmony (bug 717289), and Host clock configuration failure on Whistler. Change-Id: Ib13e87f1cd1e4dc0cd48807fedb34d952c710f68 Reviewed-on: http://git-master.nvidia.com/r/4885 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Andrew Howe <ahowe@nvidia.com> Reviewed-by: Seth Williams <swilliams@nvidia.com> Tested-by: Seth Williams <swilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-10[arm tegra] whistler: enable config TEGRA_BATTERY_ODMAbhishek Aggarwal
Enabling TEGRA_BATTERY_ODM config variable to enable battery driver on whistler. Bug: 715515 Change-Id: I1e3d750f2b75ae7bfd1de30fba64e318ed8cf467 Reviewed-on: http://git-master/r/4841 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
2010-08-10[arm tegra odm] battery: new driver for whistlerAbhishek Aggarwal
Implementing new dummy odm battery driver for whistler. It is based on the stub driver and returns success from all the relevant APIs to prevent failure of probe of tegra-battery driver. If there is no battery driver then MSD cannot be turned on. Bug: 715515 Change-Id: I2dece8b7b3d27292a96e9e59d175679b75cc13a1 Reviewed-on: http://git-master/r/4840 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
2010-08-09[arm tegra] power: proper error handling in battery probeAbhishek Aggarwal
If the open of tegra odm battery driver fails, we are failing the probe of tegra-battery without unregistering the tegra power supplies which causes errors during boot. Fixed this by moving the call to open tegra odm battery driver and its failure check before we register tegra power supplies. Bug 715515 Change-Id: Ie11c860fa692b3b707ce79796e2713366107bdec Reviewed-on: http://git-master/r/4839 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Phillip Smith <psmith@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-09[ARM] whistler: Enable USB_ANDROID_MASS_STORAGE.Rakesh Iyer
Bug 707720. Change-Id: I5a1724adae2edb19d4e20be286002a6a2d2e0e44 Reviewed-on: http://git-master/r/4937 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-08[arm/tegra] suspend: Disable A03 LP0 WAR for A03P chipKasoju Mallikarjun
Updated A03 LP0 WAR so that it is not invoked for A03P chip. Bug 713150 Change-Id: I466cc6a600e46a1ea07191a69911e44279bf4fd7 Reviewed-on: http://git-master/r/4898 Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-06[arm/tegrar]serial:Make sure dma status updated before dma stop.tegra-10.8.1Laxman Dewangan
Sometimes, when uart ask for the dma for get the number of bytes transferred by dma, the dma does not return the actual number of bytes transffred, it returns the less number of byes (less by burst size) and so uart driver client gets the data loss in communication. So to avoid the race condition, the driver stops the incoming data by making RTS line to inactive and wait for some time to complete the dma burst and then ask dma to get number of bytes transffred by dma from fifo to memory. Change-Id: I08de955fde77431115626bd884b68c8e42d52270 Reviewed-on: http://git-master/r/4832 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-06[arm/tegra]AES: Disabling custom SSK support for AP20 AO3 chipKasoju Mallikarjun
AP20 A03 LP0 WAR cannot support custom SSK. So, disabling customer SSK support for AP20 AO3 chip. Bug 714957 Change-Id: I14b21b55aae878d43be7c76584ae58af10883c13 Reviewed-on: http://git-master/r/4551 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Phillip Smith <psmith@nvidia.com> Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-06tegra fuse: correcting error handlingVenu Byravarasu
With this change: 1. corrected error handling in case of failures in FUSE_SET macro. 2. Reverted changes done to make sysfs-read of SecBootDeviceConfig fuse GfShell compatible. Tested on Whistler bug 715134 Change-Id: I7c4b57e6e3abb116e53c1da887d268375ce32a5d Reviewed-on: http://git-master/r/4805 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Vinod Atyam <vatyam@nvidia.com> Tested-by: Vinod Atyam <vatyam@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-06[arm/tegra] dma: Using the irqsave spin lock in ist.Laxman Dewangan
In place of using the simple spin_lock()/spi_unlock() in the interrupt thread, using the spin_lock_irqsave() and spin_unlock_irqrestore(). The lock is shared between the normal process context and interrupt context. Change-Id: I2c905b1daf31568919854b59d52620f06fdf10ea Reviewed-on: http://git-master/r/4838 Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-05[ARM/tegra] RM: Updated hotplug request timing.Alex Frid
Used microsecond timer to track CPU1 On/Off delays, instead of DVFS tick count (the latter can be stopped in LP2, resulting in CPU1 hotplug request extension). Set On/Off delay to 1.5sec/1.0sec, respectively. Change-Id: Idde0173f90041796ffcc0b26d865b46a48a27864 Reviewed-on: http://git-master.nvidia.com/r/4743 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-05[arm/tegra] Serial: Fixing tx trigger level setting.Laxman Dewangan
On tegra uart, the FCR setting for different tx trigger level is not same as the 16550 tx trigger level setting. The tegra uart have the setting in reverse direction on tx fifo attention level: b00 for 16 bytes attention level. b01 for 8 byte attention level. b10 for 4 byte attention level b11 for 1 byte attention level. The rx trigger attention level match with the standard uart FCR register setttings. Also fixing the typo in code when setting DTR. bug 717072 Change-Id: I3e5230de71652e3216949734f4eaca8b85e03d99 Reviewed-on: http://git-master.nvidia.com/r/4753 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-05[arm/tegra] board-generic: added support for IFX spi protocol driverSheshu Shenoy
Change-Id: Ifeb59cbd1e9b66c6409d1d7242676eac32ccb9fc Reviewed-on: http://git-master/r/4288 Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-04tegra odm pmu: Add missing setting settle time for HDMI DDCHoang Pham
There is missing setting settle time for HDMI DDC after enable. This is causing EDID read fail for some TVs on Harmony platform due to this power rail not stable after enable. After measured from scope, there is required at least 500us to make HDMI DDC stable after enable. Bug 710476 Change-Id: Ia3641896a36bce3fe9d7dda44a48721f324afb6a Reviewed-on: http://git-master/r/4737 Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-04[arm/tegra] serial: write accessor should not add read ops.Laxman Dewangan
The write accessor function uart_writeb() and uart_writel() is doing the read of the same address on which it is writing the data. This is causing unnecessarily read of rx fifo and so causing data loss in rx path if tx fifo is getting written by cpu. This is happening becasue of rx fifo and tx fifo address are same. Change-Id: I194363872d0fd251ddd15a40f42e58acd5ccc7a1 Reviewed-on: http://git-master/r/4746 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-04[ARM/tegra] pinmux: fix kernel crash during debugfs outputAndrew Howe
'cat sys/kernel/debug/tegra_pinmux' was crashing the kernel because the wrong register field was being checked for validity. Also, move offset addition to improve code generation for pg_readl and pg_writel. The IO_TO_VIRT macro ideally wants a constant argument. Change-Id: I6b24b1ac9034b2fedf330757ea5bed6a984af116 Reviewed-on: http://git-master/r/4545 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Andrew Howe <ahowe@nvidia.com>
2010-08-03usb gadget: restarting controller on cable connect in non-OTG modeAbhishek Aggarwal
On cable disconnect, the controller was stopped but on cable connect it was restarted only if OTG is enabled. Due to this for non-OTG mode, the USB device was not working after disconnecting and re-connecting the cable. Fixed this by restarting the controller for both OTG and non-OTG modes. Bug: 717685 Change-Id: I4ba83e96cfe9a559b203615a2d78d0ed582a20a7 Reviewed-on: http://git-master/r/4708 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-03[arm/tegra] Workaround for ARM erratum 742230Scott Williams
Description summary Under rare circumstances, a DMB instruction between 2 write operations may not ensure the correct visibility ordering of the 2 writes. Implication summary This erratum is more likely to be exhibited by code taking/releasing a semaphore. The implication of the erratum is that an external agent may observe the release of the semaphore before the new payload is visible, meaning that it can access an out-of-date value for the payload data. Workaround summary A software workaround is available, which consists in setting bit [4] in the undocumented Diagnostic register. This bit (“Disable DMB-lite”) causes the DMB to behave as a DSB, ensuring the correct ordering of the 2 writes. Requires Cortex-A9 MPCore config with 2 or more CPUs Present in r1p0 / r1p1 / r1p2 and r2p0 / r2p1 / r2p2 Bug 716466 Change-Id: Idabd534c383d157cdcdbb6e1d79e7bab77e0a36e Reviewed-on: http://git-master/r/4614 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-02[arm/tegra] Don't try to enable CoreSight on non-running CPUsScott Williams
On exit from LP2, __enable_coresite_access was called to reset the CoreSight interface and re-enable access on all CPUs. However, only CPU0 would actually be running at the time (the other CPU would still be held in reset). The attempt to unlock CoreSight on the non-running CPU would cause a stall on the APB bus while the CoreSight access timed out. The APB stall would cause SLINK DMA receiver overruns. Rather than attempting to unlock CoreSight access up front for every CPU, each CPU is now responsible for unlocking it's own access when it starts up. Bug 703311 Change-Id: Ie4611423ed72eb1cd0dbc8b7851f7a047bcffa14 Reviewed-on: http://git-master/r/4683 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com>
2010-08-02tegra-fb: add panningArthur Spence
Tegra framebuffer is double buffered (two contiguous framebuffers), so panning needs to be implemented. Each call to tegra_fb_pan_display also needs to cause a frame trigger in the case of one-shot displays. Change-Id: Ica110acd53f292505e487a0ca25adcb3f7a9d9aa Reviewed-on: http://git-master/r/4223 Tested-by: Arthur Spence <aspence@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-31[ARM/tegra] power: Added run-time LP0/LP1 selection.Alex Frid
Added sysfs node /sys/power/nvrm/core_lock to dynamically select lowest tegra power state in conjunction with static ODM query: - if ODM query specifies DeepSleep as lowest power state and core_lock is cleared, tegra platform enters DeepSleep (LP0) when system is suspended - if ODM query specifies DeepSleep as lowest power state and core_lock is set, tegra platform enters Suspend (LP1) when system is suspended - if ODM query specifies any state other than DeepSleep as lowest power state, core_lock is ignored (tegra platform follows ODM specification in suspend) Addresses bug 697619, facilitates LP0/LP1 testing. Change-Id: Id2d046ba202cf7630cff5e9b524995ec5e867eaa Reviewed-on: http://git-master/r/4127 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-30[ARM/tegra] RM: preserved core clocks in RM resume.Alex Frid
Preserved EMC, AVP, and system bus clocks during RM resume instead of setting them to maximum. This is necessary, since some PMUs set fixed boot core voltage value after LP0, which may be below nominal. DVFS will scale the above clocks after resume along with core voltage as necessary. Change-Id: I33ad90f39696eca569bd3bd76bb3cbf72ed18681 Reviewed-on: http://git-master/r/4569 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com>
2010-07-30[ARM/tegra] RM: Updated AVP, VDE clocks scaling.Alex Frid
- Disabled support for main clock doubler as AVP clock source (h/w recommendation). Adjusted PLLP policy entries to compensate. - Extended PLLC use for AVP clock scaling into 108MHz-216MHz range to provide better granularity than PLLP is able to. - Moved VDE v-scale reference update from preview to configuration phase (synchronized with actual clock change). Still kept voltage requirement evaluation during preview, so that core voltage is increased before the change. Change-Id: Iefc1899bd57b7f0034e945239c09b5805ebebdbb Reviewed-on: http://git-master/r/4508 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com>
2010-07-30[NvRm] Fixed calculation of Blinker Timer valueVictor Ryabukhin
Fix for bug 710667 Previous calculation gave x4 times longer time interval then necessary. Also algorithm did not work correctly on odd time intervals. Change-Id: I0f123b27e8102f3f1e49e0ebf507c6a75a3abec0 Reviewed-on: http://git-master/r/4576 Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
2010-07-29[ARM/tegra] timing: Preset CPU1 lpj.Alex Frid
Preset CPU1 lpj to skip re-calibration each time CPU1 is hot-plugged. This is justified, since CPU1 is always hot-plugged at max/boot frequency. Also h/w us timer is used for kernel delays, so CPU1 lpj is irrelevant, anyway. Change-Id: I3ffb8ad67c6f8f8fe5b59fe4eaba3b1a0ae40686 Reviewed-on: http://git-master/r/4368 Reviewed-by: John David Moser <jmoser@nvidia.com> Tested-by: John David Moser <jmoser@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-29odm:Get AlwaysON prop of SDIO slot from odm query.Pavan Kunapuli
Always ON property of SDIO slot is queried from odm. Bug 703457 Change-Id: I207183b598e92306b42eab75b3395564d171a510 Reviewed-on: http://git-master/r/4383 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-29tegra video: add driver for host1x hardwareAndrew Howe
The graphics hardware modules on Tegra family of SOCs are accessed via the host1x dma and synchronization engine. This driver exposes an userspace interface for submitting command buffers to 2d, 3d, display and mpe hardware modules and accessing the module register apertures for exclusive use hardware modules. Additional features of the driver include: - interrupt-driven hardware module usage synchronization - automatic clock management for hw modules - hardware context switching for 3d registers Change-Id: I693582249597fd307526ff3c7e35889d37406017 Reviewed-on: http://git-master/r/4091 Reviewed-by: Janne Hellsten <jhellsten@nvidia.com> Tested-by: Janne Hellsten <jhellsten@nvidia.com>
2010-07-28[arm/tegra] Enabled MMC_BLOCK_DEVICE_NUMBERING.vdumpa
Enabled MMC_BLOCK_DEVICE_NUMBERING flag, which enables naming mmcblk%d after sdhci controller instance number. Change-Id: Ie12974143dda09d7ce02db37d2b79c4a43da8977 Reviewed-on: http://git-master.nvidia.com/r/4511 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-28[tegra mmc] Generate mmcblk names based on controller.vdumpa
Generate mmcblk[%d] names based on sdhci controller instance numbers. Bug 700011 Change-Id: I2be0c88f45cb2044306b1f8b8fe98ee95a800e0e Reviewed-on: http://git-master.nvidia.com/r/4274 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-25 01:17:39 +0000