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2010-08-06[arm/tegrar]serial:Make sure dma status updated before dma stop.tegra-10.8.1Laxman Dewangan
Sometimes, when uart ask for the dma for get the number of bytes transferred by dma, the dma does not return the actual number of bytes transffred, it returns the less number of byes (less by burst size) and so uart driver client gets the data loss in communication. So to avoid the race condition, the driver stops the incoming data by making RTS line to inactive and wait for some time to complete the dma burst and then ask dma to get number of bytes transffred by dma from fifo to memory. Change-Id: I08de955fde77431115626bd884b68c8e42d52270 Reviewed-on: http://git-master/r/4832 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-06[arm/tegra]AES: Disabling custom SSK support for AP20 AO3 chipKasoju Mallikarjun
AP20 A03 LP0 WAR cannot support custom SSK. So, disabling customer SSK support for AP20 AO3 chip. Bug 714957 Change-Id: I14b21b55aae878d43be7c76584ae58af10883c13 Reviewed-on: http://git-master/r/4551 Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Phillip Smith <psmith@nvidia.com> Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
2010-08-06tegra fuse: correcting error handlingVenu Byravarasu
With this change: 1. corrected error handling in case of failures in FUSE_SET macro. 2. Reverted changes done to make sysfs-read of SecBootDeviceConfig fuse GfShell compatible. Tested on Whistler bug 715134 Change-Id: I7c4b57e6e3abb116e53c1da887d268375ce32a5d Reviewed-on: http://git-master/r/4805 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Vinod Atyam <vatyam@nvidia.com> Tested-by: Vinod Atyam <vatyam@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-06[arm/tegra] dma: Using the irqsave spin lock in ist.Laxman Dewangan
In place of using the simple spin_lock()/spi_unlock() in the interrupt thread, using the spin_lock_irqsave() and spin_unlock_irqrestore(). The lock is shared between the normal process context and interrupt context. Change-Id: I2c905b1daf31568919854b59d52620f06fdf10ea Reviewed-on: http://git-master/r/4838 Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-05[ARM/tegra] RM: Updated hotplug request timing.Alex Frid
Used microsecond timer to track CPU1 On/Off delays, instead of DVFS tick count (the latter can be stopped in LP2, resulting in CPU1 hotplug request extension). Set On/Off delay to 1.5sec/1.0sec, respectively. Change-Id: Idde0173f90041796ffcc0b26d865b46a48a27864 Reviewed-on: http://git-master.nvidia.com/r/4743 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-05[arm/tegra] Serial: Fixing tx trigger level setting.Laxman Dewangan
On tegra uart, the FCR setting for different tx trigger level is not same as the 16550 tx trigger level setting. The tegra uart have the setting in reverse direction on tx fifo attention level: b00 for 16 bytes attention level. b01 for 8 byte attention level. b10 for 4 byte attention level b11 for 1 byte attention level. The rx trigger attention level match with the standard uart FCR register setttings. Also fixing the typo in code when setting DTR. bug 717072 Change-Id: I3e5230de71652e3216949734f4eaca8b85e03d99 Reviewed-on: http://git-master.nvidia.com/r/4753 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-05[arm/tegra] board-generic: added support for IFX spi protocol driverSheshu Shenoy
Change-Id: Ifeb59cbd1e9b66c6409d1d7242676eac32ccb9fc Reviewed-on: http://git-master/r/4288 Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-08-04tegra odm pmu: Add missing setting settle time for HDMI DDCHoang Pham
There is missing setting settle time for HDMI DDC after enable. This is causing EDID read fail for some TVs on Harmony platform due to this power rail not stable after enable. After measured from scope, there is required at least 500us to make HDMI DDC stable after enable. Bug 710476 Change-Id: Ia3641896a36bce3fe9d7dda44a48721f324afb6a Reviewed-on: http://git-master/r/4737 Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-04[arm/tegra] serial: write accessor should not add read ops.Laxman Dewangan
The write accessor function uart_writeb() and uart_writel() is doing the read of the same address on which it is writing the data. This is causing unnecessarily read of rx fifo and so causing data loss in rx path if tx fifo is getting written by cpu. This is happening becasue of rx fifo and tx fifo address are same. Change-Id: I194363872d0fd251ddd15a40f42e58acd5ccc7a1 Reviewed-on: http://git-master/r/4746 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-04[ARM/tegra] pinmux: fix kernel crash during debugfs outputAndrew Howe
'cat sys/kernel/debug/tegra_pinmux' was crashing the kernel because the wrong register field was being checked for validity. Also, move offset addition to improve code generation for pg_readl and pg_writel. The IO_TO_VIRT macro ideally wants a constant argument. Change-Id: I6b24b1ac9034b2fedf330757ea5bed6a984af116 Reviewed-on: http://git-master/r/4545 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Andrew Howe <ahowe@nvidia.com>
2010-08-03usb gadget: restarting controller on cable connect in non-OTG modeAbhishek Aggarwal
On cable disconnect, the controller was stopped but on cable connect it was restarted only if OTG is enabled. Due to this for non-OTG mode, the USB device was not working after disconnecting and re-connecting the cable. Fixed this by restarting the controller for both OTG and non-OTG modes. Bug: 717685 Change-Id: I4ba83e96cfe9a559b203615a2d78d0ed582a20a7 Reviewed-on: http://git-master/r/4708 Tested-by: Abhishek Aggarwal <aaggarwal@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-03[arm/tegra] Workaround for ARM erratum 742230Scott Williams
Description summary Under rare circumstances, a DMB instruction between 2 write operations may not ensure the correct visibility ordering of the 2 writes. Implication summary This erratum is more likely to be exhibited by code taking/releasing a semaphore. The implication of the erratum is that an external agent may observe the release of the semaphore before the new payload is visible, meaning that it can access an out-of-date value for the payload data. Workaround summary A software workaround is available, which consists in setting bit [4] in the undocumented Diagnostic register. This bit (“Disable DMB-lite”) causes the DMB to behave as a DSB, ensuring the correct ordering of the 2 writes. Requires Cortex-A9 MPCore config with 2 or more CPUs Present in r1p0 / r1p1 / r1p2 and r2p0 / r2p1 / r2p2 Bug 716466 Change-Id: Idabd534c383d157cdcdbb6e1d79e7bab77e0a36e Reviewed-on: http://git-master/r/4614 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-08-02[arm/tegra] Don't try to enable CoreSight on non-running CPUsScott Williams
On exit from LP2, __enable_coresite_access was called to reset the CoreSight interface and re-enable access on all CPUs. However, only CPU0 would actually be running at the time (the other CPU would still be held in reset). The attempt to unlock CoreSight on the non-running CPU would cause a stall on the APB bus while the CoreSight access timed out. The APB stall would cause SLINK DMA receiver overruns. Rather than attempting to unlock CoreSight access up front for every CPU, each CPU is now responsible for unlocking it's own access when it starts up. Bug 703311 Change-Id: Ie4611423ed72eb1cd0dbc8b7851f7a047bcffa14 Reviewed-on: http://git-master/r/4683 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com>
2010-08-02tegra-fb: add panningArthur Spence
Tegra framebuffer is double buffered (two contiguous framebuffers), so panning needs to be implemented. Each call to tegra_fb_pan_display also needs to cause a frame trigger in the case of one-shot displays. Change-Id: Ica110acd53f292505e487a0ca25adcb3f7a9d9aa Reviewed-on: http://git-master/r/4223 Tested-by: Arthur Spence <aspence@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-31[ARM/tegra] power: Added run-time LP0/LP1 selection.Alex Frid
Added sysfs node /sys/power/nvrm/core_lock to dynamically select lowest tegra power state in conjunction with static ODM query: - if ODM query specifies DeepSleep as lowest power state and core_lock is cleared, tegra platform enters DeepSleep (LP0) when system is suspended - if ODM query specifies DeepSleep as lowest power state and core_lock is set, tegra platform enters Suspend (LP1) when system is suspended - if ODM query specifies any state other than DeepSleep as lowest power state, core_lock is ignored (tegra platform follows ODM specification in suspend) Addresses bug 697619, facilitates LP0/LP1 testing. Change-Id: Id2d046ba202cf7630cff5e9b524995ec5e867eaa Reviewed-on: http://git-master/r/4127 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-30[ARM/tegra] RM: preserved core clocks in RM resume.Alex Frid
Preserved EMC, AVP, and system bus clocks during RM resume instead of setting them to maximum. This is necessary, since some PMUs set fixed boot core voltage value after LP0, which may be below nominal. DVFS will scale the above clocks after resume along with core voltage as necessary. Change-Id: I33ad90f39696eca569bd3bd76bb3cbf72ed18681 Reviewed-on: http://git-master/r/4569 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com>
2010-07-30[ARM/tegra] RM: Updated AVP, VDE clocks scaling.Alex Frid
- Disabled support for main clock doubler as AVP clock source (h/w recommendation). Adjusted PLLP policy entries to compensate. - Extended PLLC use for AVP clock scaling into 108MHz-216MHz range to provide better granularity than PLLP is able to. - Moved VDE v-scale reference update from preview to configuration phase (synchronized with actual clock change). Still kept voltage requirement evaluation during preview, so that core voltage is increased before the change. Change-Id: Iefc1899bd57b7f0034e945239c09b5805ebebdbb Reviewed-on: http://git-master/r/4508 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Sharad Ranjan <shranjan@nvidia.com> Tested-by: Sharad Ranjan <shranjan@nvidia.com>
2010-07-30[NvRm] Fixed calculation of Blinker Timer valueVictor Ryabukhin
Fix for bug 710667 Previous calculation gave x4 times longer time interval then necessary. Also algorithm did not work correctly on odd time intervals. Change-Id: I0f123b27e8102f3f1e49e0ebf507c6a75a3abec0 Reviewed-on: http://git-master/r/4576 Tested-by: Victor Ryabukhin <vryabukhin@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
2010-07-29[ARM/tegra] timing: Preset CPU1 lpj.Alex Frid
Preset CPU1 lpj to skip re-calibration each time CPU1 is hot-plugged. This is justified, since CPU1 is always hot-plugged at max/boot frequency. Also h/w us timer is used for kernel delays, so CPU1 lpj is irrelevant, anyway. Change-Id: I3ffb8ad67c6f8f8fe5b59fe4eaba3b1a0ae40686 Reviewed-on: http://git-master/r/4368 Reviewed-by: John David Moser <jmoser@nvidia.com> Tested-by: John David Moser <jmoser@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-29odm:Get AlwaysON prop of SDIO slot from odm query.Pavan Kunapuli
Always ON property of SDIO slot is queried from odm. Bug 703457 Change-Id: I207183b598e92306b42eab75b3395564d171a510 Reviewed-on: http://git-master/r/4383 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-29tegra video: add driver for host1x hardwareAndrew Howe
The graphics hardware modules on Tegra family of SOCs are accessed via the host1x dma and synchronization engine. This driver exposes an userspace interface for submitting command buffers to 2d, 3d, display and mpe hardware modules and accessing the module register apertures for exclusive use hardware modules. Additional features of the driver include: - interrupt-driven hardware module usage synchronization - automatic clock management for hw modules - hardware context switching for 3d registers Change-Id: I693582249597fd307526ff3c7e35889d37406017 Reviewed-on: http://git-master/r/4091 Reviewed-by: Janne Hellsten <jhellsten@nvidia.com> Tested-by: Janne Hellsten <jhellsten@nvidia.com>
2010-07-28[arm/tegra] Enabled MMC_BLOCK_DEVICE_NUMBERING.vdumpa
Enabled MMC_BLOCK_DEVICE_NUMBERING flag, which enables naming mmcblk%d after sdhci controller instance number. Change-Id: Ie12974143dda09d7ce02db37d2b79c4a43da8977 Reviewed-on: http://git-master.nvidia.com/r/4511 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-28[tegra mmc] Generate mmcblk names based on controller.vdumpa
Generate mmcblk[%d] names based on sdhci controller instance numbers. Bug 700011 Change-Id: I2be0c88f45cb2044306b1f8b8fe98ee95a800e0e Reviewed-on: http://git-master.nvidia.com/r/4274 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-28mutex: Don't spin when the owner CPU is offline or other weird casesBharat Nihalani
Due to recent load-balancer changes that delay the task migration to the next wakeup, the adaptive mutex spinning ends up in a live lock when the owner's CPU gets offlined because the cpu_online() check lives before the owner running check. This patch changes mutex_spin_on_owner() to return 0 (don't spin) in any case where we aren't sure about the owner struct validity or CPU number, and if the said CPU is offline. There is no point going back & re-evaluate spinning in corner cases like that, let's just go to sleep. Cherry-picked commit: 4b402210486c6414fe5fbfd85934a0a22da56b04 URL: http://android.git.kernel.org/?p=kernel/linux-2.6.git;a=summary Kernel version picked from: v2.6.34 Re-enable HAVE_DEFAULT_NO_SPIN_MUTEXES as root-cause of spin-lock is now fixed in sched.c For bug 713808 Change-Id: I06a7c85aa46be3cdd27da0a4e62ffa442a9805b4 Reviewed-on: http://git-master/r/4500 Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-28[tegra ALSA] Add Suspend/Resume callbacksManjula Gupta
Adding stub callbacks for suspend/resume. For Bug 695593 Change-Id: Ic8ece5f87ac98094b9aeeea43e5265cdbd218f26 Reviewed-on: http://git-master/r/4460 Tested-by: Manjula Gupta <magupta@nvidia.com> Reviewed-by: Vijay Mali <vmali@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-07-28[tegra ALSA] Handle EOS event case.Manjula Gupta
Audiofx sends notification of EOS event instead of bufferdone event, if it doesn't have buffer ready to feed the record application, adding this case in the Notifier Thread of ALSA to avoid falling it under default case. For bug 714478 Change-Id: I2e48d11ce6ad40a2d2ed5241c0b9089c372507b8 Reviewed-on: http://git-master/r/4411 Reviewed-by: Vijay Mali <vmali@nvidia.com> Tested-by: Manjula Gupta <magupta@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-07-27[arm/tegra] Driver for internal RTC and alarmJon Mayo
Implementation using internal RTC(real time clock). Alarm wake up from lp0/lp1 is supported. Use option CONFIG_RTC_DRV_TEGRA to enable. Tested as working on E1108 A02 and E1109 A01 boards. Bug: 607035 Change-Id: I4c048439fd87f7df1918983f565dc7ca566fdf4c Reviewed-on: http://git-master.nvidia.com/r/3899 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-27mmc: SDHCI_INT_DATA_MASK typo errorZhangfei Gao
Signed-off-by: Zhangfei Gao <zgao6@marvell.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Cc: <linux-mmc@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Change-Id: Ie20a9aea9ac6811bc6d4f0a96d60f9f226024747 Reviewed-on: http://git-master.nvidia.com/r/4482 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-07-27[ALSA] Fix SPDIF audio routing on LDKSumit Bhattacharya
On LDK audio is getting routed to both SPDIF and headset when HDMI is connected. Fix this issue by handling audio routing properly in ALSA. Depending on available output devices ALSA will decide where to route audio. Order of preference is SPDIF->HeadPhone->Speaker. Bug 709951 Change-Id: I76971f6e17cbbd9a14a5c0ca155e765e95badb68 Reviewed-on: http://git-master/r/4452 Tested-by: Sumit Bhattacharya <sumitb@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-07-27[Arm] whistler: Disable config "TEGRA_BATTERY_ODM"tegra-10.7.2Venkat Moganty
Disabling the battery config variable in the def-config file. Enabling the battery driver causing the kernel boot failure. Bug 715080 Change-Id: I729ac5cb30c1eb861ffaa8fb5f38926131aee7cb Reviewed-on: http://git-master/r/4448 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-07-27[Arm] whistler: Disable config "TEGRA_BATTERY_ODM"Venkat Moganty
Disabling the battery config variable in the def-config file. Enabling battery driver causing the kernel boot failure. Bug 715080 Change-Id: I479bb8b9611af67737a3f86d6a10bc5824c55ec4 Reviewed-on: http://git-master/r/4449 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
2010-07-26[ventana/battery] enable battery chargingSuresh Mangipudi
defconfig change to enable battery changes for ventana Change-Id: Ib4da3a7328c89b86a5557cb9255360dd7fa3df56 Reviewed-on: http://git-master/r/4362 Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-26[accelerometer]:Support on VentanaSuresh Mangipudi
removed the BoardID based identification, now use only Peripheral GUID for determining if the board supports accelerometer or not Change-Id: I95938ff4836cbb0bb8547e2d9684dfb534816bfc Reviewed-on: http://git-master/r/4031 Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-26[ventana]Battery charging.Suresh Mangipudi
The GPIO port R pin 6 needs to be set low for charging of battery on ventana rev C Change-Id: I2ac17494f65f550d5bf676ae8ec09819983b72ac Reviewed-on: http://git-master/r/4171 Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-26[arm/tegra]spi: Fifo should be empty before starting transfer.Laxman Dewangan
It is recommended by ASIC to make sure that fifos are empty before starting any new transfer specially dma based transfer. Adding support code for this. Change-Id: Ic6b5db650b50e664b5cdd601eed9e0c3286a764b Reviewed-on: http://git-master/r/4211 Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-26[ARM] tegra: suspend: add work-around for AP20 A03 LP0 restorekrishna kishore
SDRAM initialization is broken in the boot ROM on AP20 A03, so LP0 restore needs to reload the first-stage bootloader and then jump to its LP0 restore sequence. to trigger this behavior, the lp0 flag is moved to a dummy location in the scratch register which the boot ROM ignores, but the bootloader will detect. Change-Id: Iea144e7440367938755ab66d67758558bc184b44 Reviewed-on: http://git-master/r/4022 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-07-26[ARM/tegra] power: Rescaled power timers (Part 2).Alex Frid
Fixed timer "fix" in commit c0fd286380b8b5276c7aed6fb7a9f5eacde9f60e. Removed from the LP0 entry path call to set_power_timers(), that could overwrite 32kHz-scaled timer values. This did not happen (and original "fix" worked in testing) because set_power_timers() does nothing when there is no change in APB frequency since last call, i.e., since last LP2 before LP0. Change-Id: Ida84319f26eff06d4d94f11c717fe667082bb54f Reviewed-on: http://git-master/r/4376 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-26[arm/tegra]DMA : Delayed ISR recovery routine.Victor(Weiguo) Pan
Sometimes, due to high interrupt latency in the continuous mode of DMA transfer, the half buffer complete interrupt is handled after DMA transferred the full buffer. In this case, SW DMA state and HW DMA state is out of sync. When out of sync detected, stopping DMA immediately and restarting the DMA with next buffer if next buffer is ready. bug 696953 Change-Id: Ic4b7cb251e472a309e9583eedbd26ea5dfcfceb1 Reviewed-on: http://git-master/r/4351 Tested-by: Victor (Weiguo) Pan <wpan@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[ARM] Fix race condition in kmap_high_l1_viptAndrew Howe
smp_processor_id() must not be called from a preemptible context (this is checked by CONFIG_DEBUG_PREEMPT). kmap_high_l1_vipt() was doing so. This lead to a problem where the wrong per_cpu kmap_high_l1_vipt_depth could be incremented, causing a BUG_ON(*depth <= 0); in kunmap_high_l1_vipt(). The solution is to move the call to smp_processor_id() after the call to preempt_disable(). Change-Id: I205a85ebecaedb430860462012d0571b83f08adc Reviewed-on: http://git-master/r/4342 Reviewed-by: Janne Hellsten <jhellsten@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-07-23tegra: Save CP14 registers as part of CPU suspend contextScott Williams
The CP14 (debug interface) registers were not being saved as part of the CPU suspend context. This can cause attached JTAG debuggers to lose their mind after CPU hotplug or suspend. Change-Id: Ia9cfd8a711160fd1f0852c33e3fb72f15298de85 Reviewed-on: http://git-master/r/4281 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23odmquery:remove extra check of sdio3 is_removablePavan Kunapuli
In odm query, returning the is_removable prop of sdio3 from the static array. The redundant check is removed. This is causing locking issues between kernel and nvrm. Bug 711837 Change-Id: I9d49a0f65ebb1de79d091badb0f316798c63c1cf Reviewed-on: http://git-master/r/4340 Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[arm/tegra] spi: Use native dma for data transferLaxman Dewangan
The rm spi driver is using the nvrm dma driver which is wrapper over the native dma. Using directly the native dma driver to get rid of one more level of wrapper call from spi driver. Making sure that prev dma operation is completed before starting new transfer. Removed the code which was specific to OAL as this is not required any more. Calling the write buffer barriers after writing into the write dma buffer and before starting the transmit dma to make sure that all written data is available in physical memory before dma start. Change-Id: Iabcd86f0d63b2decffda0ad6da6f1b22161e9d3b Reviewed-on: http://git-master/r/2670 Reviewed-by: Michael Hsu <mhsu@nvidia.com> Tested-by: Michael Hsu <mhsu@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[tegra-udc] Fix remove mutex call from spin_locks.Venkat Moganty
Regulator current limit uses mutex, which is called from the irq after acquiring the spin locks. Similarly when vbus is detected phy clock enable is called, which uses mutex inside the spin locks. This is fixed by calling these apis under work when called from interrupt context. Bug 711837 Change-Id: Ib926ad33d3d3674353447b3d94ff63f9eecf6f65 Reviewed-on: http://git-master/r/4339 Tested-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Tested-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Frank Cheng <fcheng@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23tegra spi: added support for various spi signal modesSheshu Shenoy
with out this change, we would only support signal mode 0... Change-Id: I2cd2c9a3e30da94f2e95a654f3154fd33e940f13 Reviewed-on: http://git-master/r/4286 Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[ARM/tegra] power: Rescaled power timers on LP0 entry.Alex Frid
Rescaled CPU power timers to 32kHz clock on entry to LP0 (before these timers were rescaled only on entry to LP1, but power off timer does affect LPO as well). Change-Id: Ifb316170a1225767f3e9b9033b5f5cb0999504d4 Reviewed-on: http://git-master/r/4349 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Iqbal Bhinderwala <iqbalb@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[ventana]:enable HDMI by setting GPIO state.Suresh Mangipudi
Setting the gpio to Input mode for the HDMI. Change-Id: If8eebb714bf09450ebaf5cae924e2b5cae4048df Reviewed-on: http://git-master/r/3771 Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Tested-by: Venkata Nageswara Penumarty <vpenumarty@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[ventana] lp0 supportSuresh Mangipudi
Set 2 sources of wake up, for ventana 1. PWR key 2. WAKE key Added support for reading the odm option for the low power state from the odm data that is provided during nvflash. Change-Id: Ib8da228a89bb514f1bce2f4971e432c269cd80ea Reviewed-on: http://git-master/r/4187 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-07-23[ARM/tegra] configuration: set LP2 config options.Alex Frid
Set LP2 configuration options for NV platforms. Change-Id: I5fcf1192f0b30774496ddcc95ca71e9613a7aecc Reviewed-on: http://git-master/r/4233 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
2010-07-23[arm/tegra] dma: Interupt thread should be smp safe.Laxman Dewangan
The interrupt thread handler have the static variable inside a function. This is causing the corruption in the variale when two processor execute the interrupt thread at same time in smp mode. Removing the qualifier static of a variable as this is not required and also safe in smp mode. Change-Id: I43fdab81a0a71c82e67eb4c12be0826f3bd8a927 Reviewed-on: http://git-master/r/4300 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
2010-07-23[arm/tegra] ODM: adding csr and broadcom GUIDrgoyal
Added GUID for broadcom and csr to identify which BT chip is present. Change-Id: Ib4163d2aacd97700047be4f20b66fc40d7aa1a35 Reviewed-on: http://git-master/r/4238 Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com> Tested-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-26 16:04:06 +0000