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put the imx6sx-19x19-arm2-gpmi-weim.dts to the common dts dir
Signed-off-by: Jason Liu <r64343@freescale.com>
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supported NAND on i.MX6SX 19x19 ARM2 board.
Signed-off-by: Allen Xu <b45815@freescale.com>
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This reverts commit 920fa48dd74b158e8a359cc546cf9f6cbfcd95a9.
[Beta2 release does not include Bug fix patches]
Signed-off-by: Jason Liu <r64343@freescale.com>
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QSPI chip changed from spansion s25fl128s to micron n25q256a
Signed-off-by: Allen Xu <b45815@freescale.com>
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i.MX6SX TO1.2 ROM has add ocram_s space support for ARM resume,
so no need to enable ROMCP to workaround it for TO1.2.
Signed-off-by: Anson Huang <b20788@freescale.com>
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On imx6sx-sdb-revb board we use pfuze200 and pfuze100 on reva board.
Signed-off-by: Robin Gong <b38343@freescale.com>
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Commit 63288b721a80 ("ARM: imx: fix shared gate clock") attempted to fix
an issue with particular enable/disable sequence from two shared gate
clocks. But unfortunately, while it partially fixed the issue, it also
did something wrong in .is_enabled() function hook. In case of shared
gate, the function shouldn't really query the hardware state via
share_count, because the function is trying to query the enabling state
of the clock in question, not the hardware state which is shared by
multiple clocks.
Fix the issue by returning the enable_count of the clock itself which is
maintained by clock core, in case it's a clock sharing hardware gate
with others. As the result, the initialization of share_count per
hardware state is not needed now. So remove it.
shawn.guo: cherry-pick commit 9e1ac462b982 from upstream
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Fixes: 63288b721a80 ("ARM: imx: fix shared gate clock")
Cc: <stable@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The CAN transceiver is changed on RevB board and the default imx6sx-sdb.dts
is for support new RevB board.
This patch adds the dts for legacy RevA board support, especially for CAN
device.
This is for people who still wants to use RevA board with this code base.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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With this, we can pass the gpio active flag from device tree
for initialize the transceiver.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Rootcause: doesn't get the correct mem ranges
from DT on imx6q after added imx6sx sdb pcie ep/rc
validation system support.
solution: Remove the imx6sx specification when get
the mem ranges from DT.
Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit b42f60a06c77448a8a00b961fb8035c58a5ed8a1)
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We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
mmc0: new ultra high speed DDR50 SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU08G 7.40 GiB
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 0
.....
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: unable to read partition table
The root cause is still unknown.
Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
(Still not confirmed by Sandisk)
By adding the delay, the overnight reboot test(run 2000+ times) did not
show the issue anymore. Originally it can easy show the error after about 20 times of
reboot test.
So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
unstable issue.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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the root cause is video memory mutex is not global variable,
it will cause video memory managment problem with mixed 2D/3D/VG.
kernel panic with multiple instances stress test running glesx_viv.sh.
Date: Jul 31, 2014
Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Jason Liu
(cherry picked from commit 9cec1cbd7ca2378e5c429f57d088d23d73d9c2f3)
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- the async reset input need ref clock to sync internally,
when the ref clock comes after reset, internal synced reset
time is too short , cannot meet the requirement
so, ssp_en should be asserted at least 4us after ref clock stable.
- align to the community imx pcie driver, add the about
200us delay to make sure that it can allow the pcie clks
stabilize, when pcie clks are enabled on imx6q/dl/solo.
Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit 5d9635c8d92b21bc12753517fa3e9884417b19be)
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-Update the parent of gpu2d_core for mx6dl.
-Update the parent of gpu3d_shader and gpu3d_core for mx6dl.
-Update the clock of gpu3d_shader and gpu3d_core for mx6dl.
The code change is cherry-picked from patch 00e75bcba16d.
Signed-off-by: Loren Huang <b02279@freescale.com>
(cherry picked from commit 2b335e6232b807d114a5a57e0b5956ab794786a4)
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Fix a build error for built-int modules do to missing inline declaration
Signed-off-by: Oliver Brown <oliver.brown@freescale.com>
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When ci core driver enable runtime pm in probe, it's possible runtime suspend
will be started before otg fsm queue work get to run, in this case, host has not
been started yet so ci->hcd is NULL, but suspend routine will access it for save
ehci registers, which result in kernle panic, this patch adds pointer valid check.
Signed-off-by: Li Jun <b47624@freescale.com>
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disabling TE/RE"
Patch "ASoC: fsl_sai: Reset FIFOs after disabling TE/RE" may accidentally
increase the underrun rate of SAI.
To keep an equal quality as previous release, we decide to revert this patch
and find a thorough way to reset the FIFO later.
This reverts commit b85f840a60de8d0a5ca8fbe7eda15f611ff5b622.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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only enable this module in specific dts file.
Signed-off-by: Allen Xu <b45815@freescale.com>
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Add new dts file and enable gpmi module.
Signed-off-by: Allen Xu <b45815@freescale.com>
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In MMC driver, two variables: boot_config and part_config are used to
keep eCSD(179) PARTITION_CONFIG. The part_config is not updated when
set new boot_config, which causes the eCSD(179) is overwritten by
any following partition switching, so the new boot_config is lost.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ed6ae43d513d211aba3ab6218feebbccbc33bdbd)
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In the rx irq handling part, we should clear the flags in RCSR not TCSR.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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SAI will not clear their FIFOs after disabling TE/RE. Therfore, the driver
should take care the task so as not to let useless data remain in the FIFO.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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There is 2s delay for controller resume from usb wakeup case already,
in OTG fsm mode, A-dev can start a new session via sys input file(means
not via usb wakeup), in this case, A-dev still need the 2s delay for
host root hub access registers, otherwise system will hang due to access
register at low power mode.
Signed-off-by: Li Jun <b47624@freescale.com>
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[<80013b00>] (unwind_backtrace+0x0/0xf4) from [<80011524>] (show_stack+0x10/0x14)
[<80011524>] (show_stack+0x10/0x14) from [<8026bc4c>] (Ldiv0+0x8/0x10)
[<8026bc4c>] (Ldiv0+0x8/0x10) from [<802c1144>] (pxp_dispatch_thread+0xd74/0x11f8)
[<802c1144>] (pxp_dispatch_thread+0xd74/0x11f8) from [<80046a90>] (kthread+0xb4/0xb8)
[<80046a90>] (kthread+0xb4/0xb8) from [<8000e118>] (ret_from_fork+0x14/0x3c)
This is caused by div by 0 in some corner cases. So add the
check before doing the division.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
(cherry picked from commit 2a5dfad5ff763d4eb8b33628ea96291ad4b95d5e)
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Just as what the V4L2 PXP does, we should pass the drect
w/h and output w/h accroding to the rotation angle.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
(cherry picked from commit bf95e3ee4131ce3ee78050f098704588766e8b07)
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System will hang if calling fb_new_modelist() function from mxc_hdmi
driver.
In the function of fbcon_new_modelist(), pointer variable vc is missing
null pointer check, add null pointer check vc to fix the issue.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Issue reproduce steps:
1. Boot up without HDMI cable plugin
2. Insert the HDMI cable.
3. echo mem > /sys/power/state , enter suspend,
4. resume it,
System can resume from suspend but display is blank.
Error log:
mxc_sdc_fb fb.31: Unable to allocate framebuffer memory
detected fb_set_par error, error code: -12
In mxc hdmi driver, if system bootup without hdmi cable plugin,
driver will create a default modelist.
In fbcon driver, array fb_display[] initialized when system bootup
and save current mode pointer that point to default modelist.
When hdmi cable is plugin the modelist will rebuild according edid
data, but the pointer of video mode in fb_display[] is not updated.
When system resume, fbcon will use the invalidate pointer to
configured framebuffer, framebuffer will crash.
Add function fb_new_modelist() after modelist is rebuild to fix the
issue.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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The QuadSPI driver has a workaround to check if M4 is using QuadSPI NOR
flash. When M4 is running on QuadSPI NOR, the QuadSPI driver will quit.
This workaround has a bug when system booting from QuadSPI NOR.
Therefore, removed the workaround and disabled the QuadSPI driver in
MCC specific DTB. The MCC DTB will let the QuadSPI driver to disabled,
not conflict with M4.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 6733ca3382ddb6358f4ccf8dd4f16d8f65995241)
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M4 has occupied the ADC1 and ADC2 in RDC, must disable them in DTS
to avoid kernel boot panic.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 046b1c214af6740e7936aae6876941e79c10da8e)
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enable dual camera support on imx6sx-sdb.
For camera ov5640, need an adapter (sch 700-28342)
For VADC, need expansion board (sch 700-26109)
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Robby Cai <r63905@freescale.com>
(cherry picked from commit ce4e36b59f225b3af75ba04accde746049a58cb4)
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The code incorrectly attempts to set the parent of periph2_clk to periph2_clk2_sel.
Fix this by calling the clk_set_parent() function with the correct parameters.
Also replace all calls to clk_set_parent() and clk_set_rate() with imx_clk_set_parent()
and imx_clk_set_rate() function that prints out error messages in case of failure.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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for PLL clocks"
The commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154, which added a check
to prevent pll rate changes when PLL is enabled, causes incorrect reporting
of MMDC clock during low power IDLE.
So revert the patch as the code needs to be improved to handle all cases.
Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks"
This reverts commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate
calls in imx6 clock driver's initialization. They are called without
retunr check. If there is something going wrong with the calls, they
will just fail silently.
The patch creates a set of helper functions imx_clk_enable_prepare,
imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock
initialization to check the return and print error message to tell
failures if any.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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GPIO17 is used by headphone jack. if don't config the PAD setting, the
gpio value is not correct.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
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Vadc need time to auto standards detection,
the default standard is NTSC, if vadc connect to PAL
camera and no enough time to detect the video mode,
driver will get NTSC mode.
Confirmation from chip design architecture auto detect function
is not required by rear-view camera application.
Setting register vdec_stddbg standard_filte bits to 0
makes the standard detection faster, the issue duplicate
decrease to 1%.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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On imx6dl dcic2 clock gate depend on dcic1,
so setting dcic1 as disp-axi clock for dcic2 in imx6qdl dts.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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396MHz in low power idle.
In low power IDLE mode, CPU needs to be sourced from PLL1 instead of PLL2_PFD0
as PLL2 needs to be in bypass mode to achieve 24MHz DDR frequency.
The original code attempts to relock the PLL1 at frequency that is as close
as possible to 396MHz, which results in PLL1 at 648MHz and the ARM freq turns
out to be 324MHz instead of 396MHz. This causes issues with CPUFREQ as 324MHz is
not a frequency listed in the cpufreq table in the device tree.
This patch attempts to fix this mis-match and maintains CPU freq at 396MHz
in low power idle.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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The recent addition of the USB audio mixer suspend/resume may lead to
deadlocks when the driver tries to call usb_autopm_get_interface()
recursively, since the function tries to sync with the finish of the
other calls. For avoiding it, introduce a flag indicating the resume
operation and avoids the recursive usb_autopm_get_interface() calls
during the resume.
Reported-and-tested-by: Bryan Quigley <gquigs@gmail.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
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The suspend callback of usb-audio driver may be called multiple times
per suspend when multiple USB interfaces are bound to a single sound
card instance. In such a case, it's superfluous to save the mixer
values multiple times. This patch fixes it by checking the counter.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
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Instead of SNDRV_DEV_LOWLEVEL, use SNDRV_DEV_CODEC type for mixer
objects so that they are managed in a proper release order.
No functional change at this point.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
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Implement reset_resume callback so that the mixer values are properly
restored. Still no boot quirks are called, so it might not work well
on some devices.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
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mode by default"
Since uart SDMA can work for Atheros BT module in android environment,
the previous patch (commit f337845718) disable SDMA mode in default,
now revert the patch to avoid the big change in dts for all platforms.
By default, we enable SDMA mode for uart.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Controls the CTS pin when the CTSC bit is negated. CTS has no
function when CTSC is asserted. After The CTS pin is low, it
needs to enable CTSC.
The patch just fix the issue.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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Start rx_dma once RXFIFO is not empty that can avoid dma request lost
and causes data delay issue.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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For DMA tx path, there have no sync between prepare the tx BD and
dma callback which can ensure tx_wor submit next dma request after
the last finished.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
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Use workque to submit tx dma request to increase tx performance.
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
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non-otg mode
This patch adds condition check for gadget disconnect when restore udc,
if in otg fsm mode, let otg fsm handle this by otg state machine.
Signed-off-by: Li Jun <b47624@freescale.com>
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If cdev->req was queued when remove composite driver, usb_ep_free_request
cannot free it, this request may get to run its completion function next time
this gadget driver load again, but the memory of completion function symbol is
invalid after the driver removal, which will result in kernel panic like below:
... ...
ci_hdrc ci_hdrc.0: enabling a non-empty endpoint!
root@imx6sxsabresd:~# Unable to handle kernel paging request at virtual address 7f02eb2c
pgd = 80004000
[7f02eb2c] *pgd=a8b41811, *pte=00000000, *ppte=00000000
Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
Modules linked in: g_ncm libcomposite configfs ov5642_camera ov5640_camera evbug [last unloaded: configfs]
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.31-daily-02005-g914c72a #20
task: 80c7b5c8 ti: 80c70000 task.ti: 80c70000
PC is at 0x7f02eb2c
LR is at _ep_nuke+0xdc/0x118
pc : [<7f02eb2c>] lr : [<803e6a90>] psr: 200f0193
sp : 80c71d30 ip : 00000000 fp : a8c1513c
r10: a803f608 r9 : 00000000 r8 : a803f5d0
r7 : a8c15134 r6 : a8c1513c r5 : a8c1513c r4 : a8c15100
r3 : 7f02eb2c r2 : 00010101 r1 : a8c15100 r0 : a803f5d0
Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: a92a804a DAC: 00000015
Process swapper/0 (pid: 0, stack limit = 0x80c70238)
Stack: (0x80c71d30 to 0x80c72000)
1d20: a803f010 ffffffea 00000001 c08661ac
1d40: 00000000 0000004b a8008900 a803f2f0 a803f010 803e7934 80c71d94 80047614
1d60: 00000000 00000001 80c784e4 a803f010 a803f014 80c83290 81545c00 00000000
1d80: 803e6be0 a803f150 80c6ec00 81545c00 00000000 a803f010 a8008950 00000000
1da0: 00000000 0000004b a8008900 80cc47ce 00000001 803e4810 803e47c0 a83a3140
1dc0: a8008950 80076be0 12d4bd61 00000000 00989680 a8008900 a8008950 a83a3140
1de0: c0802100 80c70000 00000000 80c70000 80c70000 80076d44 a8008900 a8008950
1e00: 80c71f20 80079a10 8007998c 0000004b 0000004b 800763a8 80c6def0 8000e948
1e20: c080210c 80c78904 80c71e48 80008558 800306d8 800306e8 200f0113 ffffffff
1e40: 80c71e7c 8000dc80 00000000 00000000 00000101 80c70000 00000202 00000057
1e60: 00000000 80c72080 80c70000 00000000 80c70000 80c70000 80d072c0 80c71e90
1e80: 800306d8 800306e8 200f0113 ffffffff 00000057 a8009240 80cc47ce 80c6d7a0
1ea0: 00000000 0000000a 80d072c0 80c720c0 ffffac69 80c70010 80c80564 00200000
1ec0: 80c70000 600f0193 00000057 00000000 c0802100 00000000 00000000 80c70000
1ee0: 80c70000 800308b4 80c70030 80030b50 80c6def0 8000e94c c080210c 80c78904
1f00: 80c71f20 80008558 8005cfc0 8044a8bc 600f0013 ffffffff 80c71f54 8000dc80
1f20: 80c71f68 00000055 05ffdea3 00000014 05fc1b18 00000014 81545130 80c7dd68
1f40: 00000000 00000000 80c70000 80c70000 00000017 80c71f68 8005cfc0 8044a8bc
1f60: 600f0013 ffffffff 05ffdea3 00000014 80d1c98c 80c70000 81545130 80d1c98c
1f80: 00000000 80c7dd68 00000000 8044a9fc 00000000 80c78564 806493ac 80c70000
1fa0: 80cc47ba 80c70000 80cc47ba 8000ec68 0000cf94 8005c894 80c70000 80c78480
1fc0: 00000000 80c26a9c ffffffff ffffffff 80c26548 00000000 00000000 80c61770
1fe0: 10c53c7d 80c784e0 80c6176c 80c7c3c4 8000406a 80008074 00000000 00000000
[<803e6a90>] (_ep_nuke+0xdc/0x118) from [<803e7934>] (udc_irq+0x5c8/0xcf4)
[<803e7934>] (udc_irq+0x5c8/0xcf4) from [<803e4810>] (ci_irq+0x50/0x118)
[<803e4810>] (ci_irq+0x50/0x118) from [<80076be0>] (handle_irq_event_percpu+0x54/0x17c)
[<80076be0>] (handle_irq_event_percpu+0x54/0x17c) from [<80076d44>] (handle_irq_event+0x3c/0x5c)
[<80076d44>] (handle_irq_event+0x3c/0x5c) from [<80079a10>] (handle_fasteoi_irq+0x84/0x14c)
[<80079a10>] (handle_fasteoi_irq+0x84/0x14c) from [<800763a8>] (generic_handle_irq+0x2c/0x3c)
[<800763a8>] (generic_handle_irq+0x2c/0x3c) from [<8000e948>] (handle_IRQ+0x40/0x90)
[<8000e948>] (handle_IRQ+0x40/0x90) from [<80008558>] (gic_handle_irq+0x2c/0x5c)
[<80008558>] (gic_handle_irq+0x2c/0x5c) from [<8000dc80>] (__irq_svc+0x40/0x70)
Exception stack(0x80c71e48 to 0x80c71e90)
1e40: 00000000 00000000 00000101 80c70000 00000202 00000057
1e60: 00000000 80c72080 80c70000 00000000 80c70000 80c70000 80d072c0 80c71e90
1e80: 800306d8 800306e8 200f0113 ffffffff
[<8000dc80>] (__irq_svc+0x40/0x70) from [<800306e8>] (__do_softirq+0xc8/0x200)
[<800306e8>] (__do_softirq+0xc8/0x200) from [<800308b4>] (do_softirq+0x50/0x58)
[<800308b4>] (do_softirq+0x50/0x58) from [<80030b50>] (irq_exit+0x9c/0xd0)
[<80030b50>] (irq_exit+0x9c/0xd0) from [<8000e94c>] (handle_IRQ+0x44/0x90)
[<8000e94c>] (handle_IRQ+0x44/0x90) from [<80008558>] (gic_handle_irq+0x2c/0x5c)
[<80008558>] (gic_handle_irq+0x2c/0x5c) from [<8000dc80>] (__irq_svc+0x40/0x70)
Exception stack(0x80c71f20 to 0x80c71f68)
1f20: 80c71f68 00000055 05ffdea3 00000014 05fc1b18 00000014 81545130 80c7dd68
1f40: 00000000 00000000 80c70000 80c70000 00000017 80c71f68 8005cfc0 8044a8bc
1f60: 600f0013 ffffffff
[<8000dc80>] (__irq_svc+0x40/0x70) from [<8044a8bc>] (cpuidle_enter_state+0x50/0xe0)
[<8044a8bc>] (cpuidle_enter_state+0x50/0xe0) from [<8044a9fc>] (cpuidle_idle_call+0xb0/0x148)
[<8044a9fc>] (cpuidle_idle_call+0xb0/0x148) from [<8000ec68>] (arch_cpu_idle+0x10/0x54)
[<8000ec68>] (arch_cpu_idle+0x10/0x54) from [<8005c894>] (cpu_startup_entry+0x104/0x150)
[<8005c894>] (cpu_startup_entry+0x104/0x150) from [<80c26a9c>] (start_kernel+0x324/0x330)
Code: bad PC value
---[ end trace 71c853bf79d571a9 ]---
Kernel panic - not syncing: Fatal exception in interrupt
Rebooting in 60 seconds..
Signed-off-by: Li Jun <b47624@freescale.com>
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Since commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy
ldb_di_sel from clk API), the mux clock ldb_di_sel becomes unavailable
from the clock tree. The LDB driver sets up its pixel clock rate with
the help of ldb_di_sel knowledge, and thus causes problem. The net
result is the LDB pixel clock rate slows down to 50 MHz (50285714) from
the original 64 MHz (64653061) on imx6q.
The patch fixes the problem by removing the ldb_di_sel knowledge from
the clock configuration path and just setting the rate on div_sel[chno]
clock. The bonus point is that we can use chan.vm.pixelclock directly
instead of calculating the required rate we need to set on
ldb_di_sel_parent.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This is a smilar change for imx6sx clock tree as what we did for imx6q
with commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy
ldb_di_sel from clk API).
As the valid procedure of switching ldb_di_sel on imx6sx is not
available yet, we hide this buggy mux by looking at the parent selection
done by bootloader and register it statically to clock framework, so
that switching this buggy mux becomes impossible.
Also, since the bit width of ldb_di_sels is 3, we add two "dummy"
entries for ldb_di_sels to avoid out-of-bounds error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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