| Age | Commit message (Collapse) | Author |
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Add eCompass support on Sabreauto platform
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Configuration file modified to support NAND flash, SPI-NOR,
WEIM NOR and SD card on the same image.
Bootloader arguments will be used to choose between them.
Arguments on uboot are:
spi-nor
weim-nor
By default NAND is configured if neither spi-nor or weim-nor are used
Signed-off-by: Alejandro Sierra <b18039@freescale.com>
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Stress test with I2C devices occasionally caused kernel dump and panic:
==========================dump=start==========================
v4l_capture_testapp 0 TINFO :
Color space conversion YUV420->RGB565X success!
v4l_capture_testapp 0 TINFO :
Color space conversion YUV420->RGB565X success!
clean up environment...VPU interrupt received.
Unable to handle kernel paging request at virtual address ffdf401a
pgd = ba2a4000
[ffdf401a] *pgd=4fe1a811, *pte=00000000, *ppte=00000000
Internal error: Oops: 7 [#1] PREEMPT SMP
Modules linked in: mxc_v4l2_capture ipu_still ipu_bg_overlay_sdc
ipu_prp_enc ipu_fg_overlay_sdc ipu_csi_enc ov5642_camera
camera_sensor_clock [last unloaded: ipu_csi_enc]
CPU: 0 Not tainted (3.0.35-2039-g267e004 #1)
PC is at sdma_int_handler+0x144/0x1a4
LR is at sdma_int_handler+0x70/0x1a4
pc : [<802663f4>] lr : [<80266320>] psr: 60000193
sp : ba3e7ca8 ip : bfee2100 fp : 00000001
r10: 80a67200 r9 : 80acbcf0 r8 : 00000003
r7 : 00000001 r6 : 00000001 r5 : 00000002 r4 : bfee20e0
r3 : ffdf4000 r2 : 00010104 r1 : ffdf4018 r0 : bfee2104
Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment user
Control: 10c53c7d Table: 4a2a404a DAC: 00000015
Process mxc_vpu_test.ou (pid: 3277, stack limit = 0xba3e62f0)
Stack: (0xba3e7ca8 to 0xba3e8000)
7ca0: 80038f40 bfee2000 002977e3 bf9cda80
80a6724c 00000000
7cc0: 00000000 00000022 80acbcf0 80a67200 00000001 800a5cb8
0000f08f 00000000
[<802663f4>] (sdma_int_handler+0x144/0x1a4)
from [<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
[<800a5cb8>] (handle_irq_event_percpu+0x50/0x180)
from [<800a5e24>] (handle_irq_event+0x3c/0x5c)
[<800a5e24>] (handle_irq_event+0x3c/0x5c)
from [<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
[<800a81a8>] (handle_fasteoi_irq+0xbc/0x154)
from [<800a5620>] (generic_handle_irq+0x28/0x3c)
[<800a5620>] (generic_handle_irq+0x28/0x3c)
from [<80040830>] (handle_IRQ+0x4c/0xac)
[<80040830>] (handle_IRQ+0x4c/0xac)
from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
from [<800764f4>] (__do_softirq+0x4c/0x140)
[<800764f4>] (__do_softirq+0x4c/0x140)
from [<80076a90>] (irq_exit+0x94/0x9c)
[<80076a90>] (irq_exit+0x94/0x9c)
from [<8003a1b4>] (do_local_timer+0x70/0x90)
[<8003a1b4>] (do_local_timer+0x70/0x90)
from [<8003f9cc>] (__irq_svc+0x4c/0xe8)
Exception stack(0xba3e7de8 to 0xba3e7e30)
[<8003f9cc>] (__irq_svc+0x4c/0xe8)
from [<80071a88>] (vprintk+0x328/0x4a8)
[<80071a88>] (vprintk+0x328/0x4a8)
from [<804ddb28>] (printk+0x1c/0x2c)
[<804ddb28>] (printk+0x1c/0x2c)
from [<80390de0>] (vpu_ioctl+0x2cc/0x864)
[<80390de0>] (vpu_ioctl+0x2cc/0x864)
from [<800fc314>] (do_vfs_ioctl+0x80/0x54c)
[<800fc314>] (do_vfs_ioctl+0x80/0x54c)
from [<800fc818>] (sys_ioctl+0x38/0x5c)
[<800fc818>] (sys_ioctl+0x38/0x5c)
from [<8003ff80>] (ret_fast_syscall+0x0/0x30)
Code: e594101c e5943038 e0811081 e0831101 (e5d13002)
---[ end trace 82daf36a5a07d470 ]---
Kernel panic - not syncing: Fatal exception in interrupt
Rebooting in 60 seconds..
==========================dump=end==========================
This kernel dump only happened after one period of stress-test's done.
From the dump info above, we just located the issue happened in SDMA driver.
Regularly, it'd not be any problem when sdma_int_handler()'s called. But after
tracing, we found that in those occasional times, the last one irq of a channel
hadn't been responded while sdma_free_chan_resources() was already done.
sdma_free_chan_resources() should be called in the end of the procedure. Any
irq wouldn't occur after its resources're freed.
But considering about stress test, the test scripts uses "kill" cmd to close
aplay, which means pcm_free() might be called before last buffer's transmission
was finished. Plus, many modules're working in the same time during the test.
So CPU0, the only core can handle irq, would be busy with irq-handlings, while
the other CPU cores(i.e. CPU1~3) might be idle and deal with free() much faster
than CPU0's irq-handling. Then kernel panic.
Since we know, in some extreme circumstances, the irq would not be handled in
time, we can manually handle the irq ONLY IF we could still detect one irq to
the channel in the beginning of free(), right before its resources's gonna be
freed.
This Patch added checking code in the beginning of sdma_free_chan_resources()
to detect when the channel's gonna be freed if there's still one irq pended.
If so, just handle the irq manually before we free it.
Again, considering about sdma_int_handler() might be running at the same time,
and if it already cleared the value of reg but hadn't handled the irq yet, also
added code to pend free() until irq to the channel was handled.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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* Adv7180 use tvin io_init callback to configure csi0/ipu
mux settings mx6q_csi0_io_init.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
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When setup csi ic mem on the fly channel, the capture output buffer is
initialized with hard coded dummy address 0xdeadbeaf
This also causes IPU warning when use this channel:
imx-ipuv3 imx-ipuv3.0: IDMAC20's EBA0 is not 8-byte aligned
- use the pre-allocated dummy_frame.vaddress instead of 0xdeadbeaf
Signed-off-by: Sheng Nan <b38800@freescale.com>
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ioctl_s_parm for ov5642 and ov5640, it didn't check if sensor changed mode
successfully.
So it updates the sensor parameters with new framerate and new mode even
if the sensor failed to change mode.
The original framerate and mode is useful for the exposure calculation.
It should keep consistent with sensor actual work mode.
- This patch checks the return value of function which changes sensor mode
If it succeed, update sensor parameters.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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Write to the MMDC registers when resetting the MMDC after the
DDR I/Os have been floated.
This fixes the bug introduced by the commit:
"2a2f65bd07ad0f947794c2e5f2f825121805d663
MX6SL-Reset MMDC read FIFO in low power IDLE"
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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The REG_BYPASS_COUNTER(RBC) holds off interrupts when the PGC
block is sending signals to power gate the core. This is apart
from the RBC counter's basic functionality to act as counter to
power down the analog portions of the chip.
But the counter needs to be set/cleared only when no interrupts
are pending. And also for correct hold off the interrupts, enable the
counter as close to WFI as possible.
The RBC counts CKIL cycles (32KHz)
So follow the following steps to set the counter
in suspend/resume in mx6_suspend.S:
1. Mask all the GPC interrupts.
2. Write the counter value to the RBC
3. Enable the RBC
4. Unmask all the interrupts.
5. Busy wait for a few usecs to wait for RBC to start counting
in case an interrupt is pending.
4. Execute WFI
Reset the counter after resume in pm.c:
1. Mask all the GPC interrupts.
2. Disable the counter.
3. Set the RBC counter to 0.
4. Wait for 80usec for the write to get accepted.
5. Unmask all the interrupts.
With the above steps, we can minimize the PDNSCR and PUPSCR counters
in the GPC. The basic condition for the RBC counter:
RBC count >= 25 * IPG_CLK + PDNSCR_SW2ISO.
PDNSCR_SW2ISO = PDNSCR_ISO = 1 (counts in IPG_CLK)
PUPSCR_SW2ISO = PUPSCR_ISO = 2 (counts in 32K)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Lily Zhang
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Change v4l2 capture stream off sequence.
Both CSI MEM and CSI IC MEM channel wait for idmac eof and
disable csi firstly.
The disable sequence is:
- wait for idmac channel EOF, disable csi
- disable idmac channel
- disable smfc (CSI-->MEM channel)
Signed-off-by: Sheng Nan <b38800@freescale.com>
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current _ipu_csi_wait4eof only support CSI-->MEM channel
- add support of CSI_PRP_ENC_MEM
- add support of CSI_PRP_VF_MEM
Signed-off-by: Sheng Nan <b38800@freescale.com>
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The recommended sequence for disable csi is,
disable csi as soon as we get IDMAC eof interrupt.
- add wait for eof when disable csi.
- don't wait for eof when disable CSI-->MEM channel.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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current setting of 5M (QSXGA) mode, sensor works at 2.5fps.
the expected frame rate is 7.5fps.
- use new ov5642 QSXGA firmware get from ov
change sensor PLL settings 0x3010/0x3012
QSXGA frame rate changes from 2.5 -- 7.5fps
- change mode between QSXGA@15fps and VGA@15fps go through quick change path.
modify QSXGA_VGA quick change firmware due to the QSXGA PLL setting changes.
keep value of 0x3010/0x3012 the same as VGA@15fps original value.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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Fix all build warnings in files:
arch/arm/mach-mx6/board-mx6sl_common.h
arch/arm/mach-mx6/board-mx6sl_evk.c
arch/arm/mach-mx6/clock_mx6sl.c
arch/arm/mach-mx6/cpu_regulator-mx6.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/dvfs_core.c
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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If VPU is working before suspend, we need to disable its regulator
to make sure regulator can be off before suspend, then enable
its regulator before resume to work, we check vpu's open_count
to determine whether to disable/enable its regulator.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The EPDC set the UPD_VOID (i.e. cancelled) bit in two cases:
1. No pixels needed updating
2. All pixels collided (COL bit also set)
The driver was miss-handling case 2. This fix causes case 2
to be treated as a collision and the update to be resubmitted.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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MMDC can clock in bad data due to the glitches caused by
changing the setting of various DDR IO pads in low power
IDLE to save power. Solution is to reset the MMDC read FIFO
before the DDR exits self-refresh.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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In the maxim 17135 driver, the power good is confirmed by the
power good GPIO polarity change when comparing the status at
the beginning of driver probe and display regulator enabled.
However, it is not reliable since the initial value of the GPIO
is not constant. Normally, it is 1 but it can be 0 after system reset
unexpectedly. Now, it is changed to POK bit checking in FAULT register.
Signed-off-by: Jack Lee <jack.lee@freescale.com>
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If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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If "debug_uart" is specified in the command line, uart will
be sourced from 24MHz XTAL. This is required for getting the
correct power measurements on MX6SL.
Certain analog power optimizations are done only if ALL PLLs
are bypassed on MX6SL. To verify this path, we need to ensure
that UART is not sourced from PLL3.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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change ov5640_init_mode sequence according to ov's suggestion
ov5640 support two method of size switching, scaling and subsampling
exposure calculation when change size between scaling and subsampling
- scaling: image size bigger than 1280*960
- subsampling: image size smaller than 1280*960
This patch changes the sequence of ov5640_init_mode()
1. setting mipi csi2 (no change).
2. check mode
- if it is in INIT_MODE, go throught initial procedure
- if sensor changes between scaling and subsampling,
go through exposure calcualtion
- otherwise, configure mode directly.
3. other procedures keep the same.
Signed-off-by: Sheng Nan <b38800@freescale.com>
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Update the VDDARM and VDDSOC voltages based on IMX6SLCEC_Rev0
datasheet.
As the voltages for ARM @ 198MHz and ARM @ 396MHz are the same
remove the 198MHz working point.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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- XVCLK equals MCLK/10000, currently XVCLK is hard set as 2200
- rename it in lower case
Signed-off-by: Sheng Nan <b38800@freescale.com>
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remove duplicated definition of prev_sysclk
Signed-off-by: Sheng Nan <b38800@freescale.com>
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clear code type warning generated by script
Signed-off-by: Sheng Nan <b38800@freescale.com>
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1. Fix AHB clock not changed to 3MHz in IDLE mode
2. Fix system hangs in IDLE mode due to changes made for LOCKDEP
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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1. Fix mutex_lock nested issue in idle mode
2. Fix mutex_lock nested issue in suspend mode
3. Fix spin_lock nested issue in busfreq
Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
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When a 5-bit waveform is loaded, the maximum number of available
LUTs is 16. The LUT allocator must account for this.
Note that 5-bit waveform loading is currently not supported in the
driver. However, this fix makes sure the LUT allocator is correct
when 5-bit support is added.
Signed-off-by: Michael Minnick <michael.minnick@freescale.com>
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- change the delay from 10 * HZ to 1 * HZ, though (1 * HZ) might not be the
best, just as a base.
1. Since the request has been moved out of interrupt context, there will be no
more calling enable_clk in interrupt context. So it's not necessary to keep
such a long delay on disabling clock in order to save power.
2. Still keeping the 1*HZ of delay is to avoid frequently enabling/disabling
clock.
eMMC card performance test result with bonnie++:
(512M RAM, 1GB data, 1K buffer)
------------------------------------------------------------------------------
| | 1*HZ | 10 * HZ |
------------------------------------------------------------------------------
| Read | ~24.1MB/s | ~23.9MB/s |
------------------------------------------------------------------------------
| Write | ~10.5MB/s | ~10.5MB/s |
------------------------------------------------------------------------------
WiFi card performance test result with iperf is quite same: ~21Mbps
(AR6003@2.4G, TCP, TCP window size option 1MB both for server and client)
Acked-by: Robby CAI <r63905@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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There is a bug udc driver handle invalid USB_FEATURE requests in current bsp.
The invalid USB_FEATURE request will be handled as a valid USB_FEATURE request.
We should set protocol stall on ep0 to handle invalid USB_FEATURE requests.
Signed-off-by: make shi <b15407@freescale.com>
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It will cause below problem if spin_lock debug is on:
BUG: spinlock lockup on CPU#0, swapper/1, 9a0292a0
The reason is the lock is used before initialization.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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When CONFIG_LOCKDEP is enabled, it will cause warings:
------------[ cut here ]------------
WARNING: at kernel/lockdep.c:2885 sysfs_add_file_mode+0x54/0xc0()
Modules linked in:
[<80046364>] (unwind_backtrace+0x0/0xfc) from [<800758c0>]
(warn_slowpath_common+0x4c/0x64)
[<800758c0>] (warn_slowpath_common+0x4c/0x64) from [<800758f4>]
(warn_slowpath_null+0x1c/0x24)
[<800758f4>] (warn_slowpath_null+0x1c/0x24) from [<801536c4>]
(sysfs_add_file_mode+0x54/0xc0)
[<801536c4>] (sysfs_add_file_mode+0x54/0xc0) from [<8015616c>]
(internal_create_group+0xdc/0x1d8)
[<8015616c>] (internal_create_group+0xdc/0x1d8) from [<80524110>]
(fsl_otp_probe+0x168/0x1d4)
[<80524110>] (fsl_otp_probe+0x168/0x1d4) from [<802b42e8>]
(platform_drv_probe+0x18/0x1c)
[<802b42e8>] (platform_drv_probe+0x18/0x1c) from [<802b2fe4>]
(driver_probe_device+0x98/0x1a4)
[<802b2fe4>] (driver_probe_device+0x98/0x1a4) from [<802b3184>]
(__driver_attach+0x94/0x98)
[<802b3184>] (__driver_attach+0x94/0x98) from [<802b280c>]
(bus_for_each_dev+0x60/0x8c)
[<802b280c>] (bus_for_each_dev+0x60/0x8c) from [<802b2180>]
(bus_add_driver+0x190/0x268)
[<802b2180>] (bus_add_driver+0x190/0x268) from [<802b3788>]
(driver_register+0x78/0x13c)
[<802b3788>] (driver_register+0x78/0x13c) from [<800394ac>]
(do_one_initcall+0x30/0x170)
[<800394ac>] (do_one_initcall+0x30/0x170) from [<800083cc>]
(kernel_init+0x98/0x144)
[<800083cc>] (kernel_init+0x98/0x144) from [<8004003c>]
(kernel_thread_exit+0x0/0x8)
---[ end trace 877415a10b5d9cb1 ]---
also, on imx6sl, it will cause below issue:
BUG: key bffea2e4 not in .data!
BUG: key bffea300 not in .data!
BUG: key bffea31c not in .data!
BUG: key bffea338 not in .data!
BUG: key bffea354 not in .data!
BUG: key bffea370 not in .data!
BUG: key bffea38c not in .data!
BUG: key bffea3a8 not in .data!
BUG: key bffea3c4 not in .data!
BUG: key bffea3e0 not in .data!
BUG: key bffea3fc not in .data!
BUG: key bffea418 not in .data!
BUG: key bffea434 not in .data!
BUG: key bffea450 not in .data!
BUG: key bffea46c not in .data!
BUG: key bffea488 not in .data!
BUG: key bffea4a4 not in .data!
BUG: key bffea4c0 not in .data!
BUG: key bffea4dc not in .data!
We need to call sysfs_attr_init to initlize sysfs attr.
Signed-off-by: Terry Lv <r65388@freescale.com>
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If there is no nand chip in the board, the kernel will prints out the
following warning message:
------------[ cut here ]------------
WARNING: at arch/arm/plat-mxc/clock.c:63 clk_disable+0x48/0x90()
clock enable/disable mismatch! clk apbh_dma_clk
Modules linked in:
[<80044f48>] (unwind_backtrace+0x0/0xfc) from
[<80070ac0>] (warn_slowpath_common+0x4c/0x64)
[<80070ac0>] (warn_slowpath_common+0x4c/0x64) from
[<80070b6c>] (warn_slowpath_fmt+0x30/0x40)
[<80070b6c>] (warn_slowpath_fmt+0x30/0x40) from
[<8005ee60>] (clk_disable+0x48/0x90)
[<8005ee60>] (clk_disable+0x48/0x90) from
[<80255e48>] (dma_chan_put+0x4c/0x50)
[<80255e48>] (dma_chan_put+0x4c/0x50) from
[<80255f18>] (dma_release_channel+0x24/0x94)
[<80255f18>] (dma_release_channel+0x24/0x94) from
[<802ad8ec>] (release_resources+0x58/0x6c)
[<802ad8ec>] (release_resources+0x58/0x6c) from
[<80445964>] (gpmi_nand_probe+0x44c/0x4ec)
[<80445964>] (gpmi_nand_probe+0x44c/0x4ec) from
[<80281868>] (platform_drv_probe+0x18/0x1c)
[<80281868>] (platform_drv_probe+0x18/0x1c) from
[<80280590>] (driver_probe_device+0x98/0x1a4)
[<80280590>] (driver_probe_device+0x98/0x1a4) from
[<80280728>] (__driver_attach+0x8c/0x90)
[<80280728>] (__driver_attach+0x8c/0x90) from
[<8027fdd0>] (bus_for_each_dev+0x60/0x8c)
[<8027fdd0>] (bus_for_each_dev+0x60/0x8c) from
[<8027f75c>] (bus_add_driver+0x184/0x25c)
[<8027f75c>] (bus_add_driver+0x184/0x25c) from
[<80280d1c>] (driver_register+0x78/0x13c)
[<80280d1c>] (driver_register+0x78/0x13c) from
[<80022d80>] (gpmi_nand_init+0xc/0x3c)
[<80022d80>] (gpmi_nand_init+0xc/0x3c) from
[<80039478>] (do_one_initcall+0x30/0x16c)
[<80039478>] (do_one_initcall+0x30/0x16c) from
[<80008410>] (kernel_init+0x98/0x144)
[<80008410>] (kernel_init+0x98/0x144) from
[<8003ffb4>] (kernel_thread_exit+0x0/0x8)
---[ end trace c28d32057fe33a29 ]---
This mxs_dma_clk's usecount is not correctly changed which causes the kernel
shows this warning.
This patch adds proper clk_disable_unprepare/clk_prepare_enable in
the mxs-dma driver to balance the mxs_dma_clk's usecount.
Also put the mxs_dma_clk when the gpmi exits.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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There are several channels' buffer ready bits controlled
by a single 32bit register-IPU_CHA_BUFx_RDY. These buffer
ready can be write-one-to-set or write-one-to-clear, which
is controlled by IPU_GPR register. v4l2 capture driver will
touch the buffer ready registers in interrupt context, so,
currently, ipu->mutex_lock is bypassed with the context.
Then, a race condition is that v4l2 capture driver interrupt
context tries to set a channel buffer ready, while, another
context tries to disable another channel(clear buffer ready
bit), which may cause v4l2 capture driver fails to set buffer
ready(SMFC0_FRM_LOST error may happen). This patch uses ipu->
rdy_reg_spin_lock to protect buffer ready registers to fix
the race condition issue and rename ipu->spin_lock to ipu->
int_reg_spin_lock.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit d3515529a4be205809356961e58afa660781547b)
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1) We get busy_lock semaphore before we get a dqueue event, so, when user
is blocked at DQBUF ioctrl, the user will also be blocked at QBUF ioctrl,
then the video performance will drop. This patch changes to get busy_lock
semaphore to protect DQBUF ioctrl until we successfully get a dqueue event.
2) Use queue_int_lock and dqueue_int_lock spinlocks to protect working_q/
ready_q/done_q in the end of frame interrupt handler camera_callback(), in
case, the handler and VIDIOC_QBUF/VIDIOC_DQBUF ioctrls are called on diff-
erent cores at the same time.
3) Protect ready_q with queue_int_lock spinlock in mxc_streamon(), in case,
VIDIOC_STREAMON and VIDIOC_QBUF ioctrls are called on different cores at
the same time.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit e92c2307ebcf66badc5db8d4449218e3489a9e78)
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1) Change to enable/disable mclk only in open, release,
suspend and resume functions, since we may simply think that
sensor or mclk will be used soon after cam->open_count is non-zero.
2) Fix a bug when calling ipu_csi_enable_mclk_if() with wrong
parameter(cam->csi should be cam->mclk_source) in mxc_v4l2_close()
and in mxc_v4l2_s_ctrl() with V4L2_CID_MXC_SWITCH_CAM control id.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit be689b81ac24c0a4373a989664ec51ad77db0ced)
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- original VGA/XGA@15fps image has many noise.
- new ov5642 firmware can get fine quality
Signed-off-by: Sheng Nan <b38800@freescale.com>
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When suspend, the lcdif and panel will be stopped. When resume, fb_set_par()
will be called, in which the lcdif and the panel will be re-initialized.
However, fb_set_par() also checks the parameters via mxc_elcdif_fb_par_equal(),
which will probably make fb_set_par() just return with them un-initialized.
And thus, the interrupt will not come. This patch added a varible to check
whether they're running along with mxc_elcdif_fb_par_equal() checking to
fix the issue. If not running, re-initialization will be forcely done.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Add csi v4l2 platform device only when 'csi' is assigned in cmdline.
Because there's pin conflicts between csi and epdc.
Signed-off-by: Robby Cai <R63905@freescale.com>
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Because csi_v4l2 driver will only be loaded when needed(by assign 'csi' in
kernel cmdline), we use standard driver framework to easily bind the device and
driver. Otherwise, we will meet the problem like the crash as below when do
suspend/resume due to the resource of csi not assigned at all if 'csi' not
passed in cmdline.
root@freescale ~$ echo mem > /sys/power/state
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.01 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 9a8ac000
[00000000] *pgd=9a783831, *pte=00000000, *ppte=00000000
Internal error: Oops: 17 [#1] PREEMPT
Modules linked in:
CPU: 0 Not tainted (3.0.35-02115-g08f4436 #233)
PC is at csi_enable_mclk+0x40/0x68
LR is at camera_power+0x1c/0x5c
pc : [<80357f08>] lr : [<80358154>] psr: 60000013
sp : 9a8ebe30 ip : 00000009 fp : 00000006
r10: 1c6bddf7 r9 : 00000000 r8 : 00000000
r7 : 00000002 r6 : 804fd0ac r5 : 9a013000 r4 : 00000000
r3 : 80aa8bbc r2 : 00000000 r1 : 00000000 r0 : 00000008
...
Signed-off-by: Robby Cai <R63905@freescale.com>
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For DQ and DL, we must make sure DDR can be accessed after resume,
our code did NOT get a valid base address for MMDC to exit from
DVFS mode, need to fix it.
According to ARM, we only need to save r0-r3 and r12 before calling
C function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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issue:
Once entering low power idle mode, pll2_400 will be bypass which will change
the clk rate of sdhc root clk. so far, there's no mechanism to inform sdhc
for changing of root clk in current driver structure.
fix:
Revert "ENGR00226096 mx6sl: remove high set point for usdhc"
This reverts commit 97aee96a34ca63da0d1d602a19b3a444352e5803.
Acked-by: Robby CAI <r63905@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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issue:
Since there's no sync mechanism between sdio bus suspending and sdio_irq_thread,
it will cause that sdio_irq_thread still makes sdhc request even after sdio bus
suspends.
fix:
On suspending sdio bus, claim host, so that:
1. mmc_sdio_suspend will wait for finishing of sdio_irq_thread.
2. sdio_irq_thread will be blocked even being scheduled.
And release host on resuming.
Acked-by: Aisheng DONG <b29396@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
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Setup uart2 to enable bluetooth basic functionality on mx6sl evk board.
DMA mode was not enabled for uart2 operation.
Signed-off-by: Lionel Xu <Lionel.Xu@freescale.com>
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Currently, the sequence and functionality we use to enter and exit
suspend causes us to hang upon resuming. It appears that this is being
caused by two things. The first is the powering off of the 2p5 rail
which powers the IO pullups and pulldowns. The DQS pins were
configured as pull downs. The second is switching the DQS pins from
differential to CMOS mode (and back). This second problem only
occurs on a few EVK boards.
It is believed that these changes are causing glitches on the mmdc DQS
pins which is putting garbage in the FIFO (or causing some other FIFO
problem). This patch adds two mmdc0 FIFO resets after exiting the
suspend. Two are thought to be needed per previous FIFO reset
experience by Mike Kjar.
Since the MMDC0 FIFO will be cleaned each time, we can now remove
the code that configured the DQS lines as pull downs as we no
longer care if they float.
Signed-off-by: Robert Lee <robert.lee@freescale.com>
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According to the latest specification data, these rails should
go no lower than 900mV in standby mode. This patch modifies
the existing mx6sl board files and sets the pmic standby voltage
for these rails to be 925mV (extra 25mV to account for pmic accuracy).
Signed-off-by: Robert Lee <robert.lee@freescale.com>
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Need to ensure that DDR IO pads are not floated when
a peripheral that needs DDR is active, for ex SDMA.
Also need to keep IPMUX clock enabled even when ARM
is in WFI, so set the CCGR bits accordingly.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Different linker may use r12, we should save/restore all
registers(r0-r12) before calling C function to prevent
these registers from corruption in C code.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Although 400M bus setpoint can save some SOC domain power,
but it will also bring some additional power consumption
to DDR3, and the DDR performace's drop could also lead to
more heat generated by COREs which will spent more time
waiting for DDR data ready, also, there is not many usecases
that need this setpoint, all in all, we should remove 400M
setpoint.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Change STANDBY mode to support the following for MX6SL:
1. assert VSTBY
2. ARM is power gated.
3. XTAL is ON
4. LDO 2P5 is disabled, weak 2P5 is enabled.
5. LDO 1p1 is enabled.
Implement this for a higher power but lower latency on resume
from STANDBY mode.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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