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2012-09-03ENGR00222855 MX6 CPUFREQ: support three VDDSOC setpointsrel_imx_3.0.35_12.09.02Robin Gong
On MX6Q/DL , there is only two set point of VDDSOC/VDDPU, one is 1.25V(1GHz), another is 1.175V. And in arch/arm/plat-mxc/cpufreq.c will judge whether the current cpu frequency is the highest set point(1G) or not to set the right VDDSOC/VDDPU. The logic is also match to dynamic ldo bypass function, since the change point is the highest set point too. But there is three set points of VDDSOC/VDDPU in MX6SL , so the logic in cpufreq.c need to change. Now VDDSOC/VDDPU will track with VDDARM fully. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-09-03ENGR00222841: mx6sl: pgc: display power gating causes PxP processing timeoutRobby Cai
For safety, DO NOT enable display power gating feature for MX6SL EVK. Otherwise will meet PxP processing timeout when run EPDC unit test. The cause is under investigation. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-09-03ENGR00222834 MX6x-A9 prefetcher should not access DDR before IO is restoredRanjani Vaidyanathan
Add enough nops to suspend code when exiting due to a pending interrupt. This is required so that we can guarantee that the prefetch unit will not bring DDR out of self-refresh before all of the DDR's IO pads are restored. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-03ENGR00222835 MX6x-Fix incorrect enabling/disabling of PLL1Ranjani Vaidyanathan
PLL1 was enabled without incrementing the usecount, and was thus not getting disabled under certain conditions. This causes 2 issues: 1. Increases the power. 2. Causes crashes on MX6SL in audio mode as ARM is switched to PLL1 assuming its in bypass when entering WAIT mode. But PLL1 is enabled and not in bypass state. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-02ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.Ranjani Vaidyanathan
Need to ensure that no page table walk occurs in DDR when it is in self refresh and its IO pads are floated during suspend. Hence we need to make sure that the translation of all the addresses that the suspend code will access is in the TLB before DDR cannot be accessed anymore. So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters. Also need to add a dsb to drain all the write buffers before DDR enters self-refresh. Also ensure that the LDO bypass enable is reset if an interrupt is pending before the system enters suspend. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-09-02ENGR00222157 MX6x-Fix bug in transitioning from low_bus to audio_bus mode.Ranjani Vaidyanathan
Ensure that the transtion from low bus freq mode to audio bus freq mode happens instantly. Don't schedule the delayed work in this case else there will be a pause in the audio playback. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-31ENGR00222134 MX6x - Fix race-conditions in low power code.Ranjani Vaidyanathan
Fix couple of race-conditions associated with low power IDLE code: 1. Ensure that bus freq mutex is used in the suspend/resume function 2. Ensure that the usecount of pll2 is incremented/decremented when ARM is switched to run from PLL2_PFD_400. And PLL2 is enabled/disabled when necessary. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-31ENGR00222133 MX6SL - Fix crashes caused by Low power IDLE supportRanjani Vaidyanathan
Need to ensure that the ARM_CLK rate stays exactly the same when moving ARM_CLK from PLL2_PFD_400 to PLL1 when system enters 24MHz state. Also need to ensure that PLL1 is enabled before relocking the PLL to the correct rate. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-31ENGR00221370 IPUv3:Clean up IPUv3 interrupt handlerLiu Ying
1) In the interrupt handler, we access sync interrupt control registers 2 times, and each time with spin lock being held and then released, which may cause potential racing on the registers. We see that as long as the racing happens with two displays enabled on the same IPU, one IPU display channel will lose EOF interrupt and it makes its fb's pan display ioctrl fail with timeout. This patch changes to hold the spin lock one time for the whole irq handler, as the handler should return quickly. Holding and releasing the spin lock unnecessarily may bring performance penalty as well. 2) We do not need to use spin_lock_irqsave() and spin_unlock_irqrestore() in the interrupt handler, as we are already in the hard irq context. Using spin_lock() and spin_unlock() is enough to protect the registers. 3) Clear an interrupt control bit as soon as its related handler finishes. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit c5d3731fa0880a65efafb4826d3722aacb79edd5)
2012-08-30ENGR00221983 IPUv3:Correct ERR and SYNC interrupt line numbersLiu Ying
As we define ERR interrupt with 0 irq resource id and SYNC interrupt with 1 irq resource id in platform-imx_ipuv3.c, we wrongly assign them in IPUv3 driver. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 52c9fc323e0f72e53de6fe0c6f7012fe7adf14b4)
2012-08-30ENGR00221218: imx6: remove redundant spi defineRobby Cai
There're two imx6q_add_ecspi() defines, remove one. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-30ENGR00222005 mfgtool can't work on mx6sl evk boardTony LIU
- add imx6s_updater_defconfig to generate mx6sl firmware - add CONFIG_MACH_MX6SL_EVK=y - remove SMP for mx6sl - add CONFIG_MX6_INTER_LDO_BYPASS=y Signed-off-by: Tony LIU <junjie.liu@freescale.com>
2012-08-29ENGR00221975 Fix race condition in clock code.Ranjani Vaidyanathan
Need to ensure that check for usecount in clk_set_parent occurs within the protection of the clock mutex. Else there is a chance that the usecount can be decremented (and the clock disabled) after the check. Also add back the code to maintain the correct usecount for pll2_pfd_400. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-29ENGR00221974 MX6SL-Fix system hang/crash issue in low power IDLERanjani Vaidyanathan
Ensure that the pull-up is enabled when the DQS line of LPDDR2 is floated when DDR freq is dropped to 24MHz. This is required else its possible that the DDR will latch incorrect data when it exits self-refresh. CKE line should not be floated as it may cause DDR to incorrectly exit self-refresh mode. Also add 25 nops after the code that removes DDR from self-refresh. We need this to ensure that the prefetcher block in A9 does not access any instruction from DDR before the DDR exits self-refresh. The A9 prefetch depth is about 23, hence 25 nops. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-29ENGR00221970 MX6SL:Fix suspend/resume issue on MX6SLEVKRanjani Vaidyanathan
Make sure the Pull Ups are enabled on the DQS lines of LPDDR2 memory. Without that its possible that the data latched by the memory will be incorrect when exiting from self-refresh mode. So only set the drive strengths to 0 when floating the DDR IO pads before entering suspend. Also never float the CKE pad, this pin always needs to be driven, else the DDR may incorrectly exit self-refresh. Hence remove the line that was setting CKE drive strength to zero (GRP_CTLDS). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-30ENGR00221902 [MX6]Fix udelay inaccurate issue during suspend/resumeAnson Huang
When system enter suspend, we increase CPUFreq to the highest point without update the global loops_per_jiffy, it will lead to udelay inaccurate during the last phase of suspend/resume. WB counter and RBC counter need at least two 32K cycles to finish, here we add 80us for safe. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221867 sabresd : support adjust VDDSOC if enable LDO bypassRobin Gong
support adjust VDDSOC if enable LDO bypass on mx6_sabresd board Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-29ENGR00221716-02 Mx6 USB host: add port speed define MACRO to arc_otg.hmake shi
Add port speed define MACRO to arc_otg.h. Signed-off-by: make shi <b15407@freescale.com>
2012-08-29ENGR00221716-01 Mx6 USB host: set disconnect bit should wait for resume finishedmake shi
For i.MX6DLTO1.1 and i.MX6DQTO1.2, the disconnection-bit can only be set after the resume finished, otherwise, the remote-wake-up may fail. Because if the device not switch to High-Speed 45ohm termination resistors mode, when the disconnection detection bit is set the disconnection detection circuit will detect a high speed disconnection by mistake. Signed-off-by: make shi <b15407@freescale.com>
2012-08-29ENGR00182456-3 HDMI VIDEO: abort audio when unblank and plugoutChen Liangjun
In this patch: 1. Close audio PCM stream when video unblank and plugout event happens. 2. Set HDMI cable and blank state into HDMI core driver when plug/unplug, blank/unblank events happens. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-08-29ENGR00182456-2 HDMI AUDIO: register/unregister when audio pcm open/closeChen Liangjun
In this patch: 1. Register substream into HDMI core driver when HDMI audio PCM is open. 2. Unregister substream out of HDMI core driver when HDMI audio PCM is close. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-08-29ENGR00182456-1 HDMI: Add interface for HDMI audio managementChen Liangjun
In this patch, add support for: 1. Interface for HDMI audio to register PCM into HDMI core driver. 2. Interface for HDMI video driver to stop HDMI audio 3. Interface for HDMI video driver to inform the state of HDMI cable and state of HDMI blank. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-08-29ENGR00221643 [MX6]Fix race condition of pfd 400 usecountAnson Huang
We can't modify the usecount of pfd 400M clock when ARM freq is changed, as when the children of pfd 400M do clock enable/disable, they will also modify this usecount, these two modification is out of same lock protection. And this wrong usecount may lead to pfd 400M or pll2 disabled accidently, and it will cause system hang! Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-29ENGR00221438 [MX6]Adjust CPU setpoint according to datasheetAnson Huang
1. Adjust ARM/SOC/PU voltage according to latest datasheet; 2. Remove Rigel's 200M setpoint to align with Arik. Signed-off-by: Anson Huang <b20788@freescale.com>
2012-08-28ENGR00221298 Fix tuner clock frequency on SSIAlejandro Sierra
Fix clock frequency configuration on SSI interface for the Tuner driver. Signed-off-by: Alejandro Sierra <b18039@freescale.com>
2012-08-28ENGR00221689 wm8962: add wait time after enable power supplyGary Zhang
add 100ms wait time after enable power supply for power stability Signed-off-by: Gary Zhang <b13634@freescale.com>
2012-08-28ENGR00221302 [MX6SL_ARM2/EVK]: VDDSOC adjust if use LDO bypassRobin Gong
The function has been implement in LDO enable , but not in LDO bypass. Implement it on mx6sl. Signed-off-by: Robin Gong <B38343@freescale.com>
2012-08-27ENGR00221457 MX6DL clock:Set PLL3_PFD_540M to 540MHzLiu Ying
This patch sets PLL3_PFD_540M clock frequency to 540MHz so that IPU and VPU clock can reach 270MHz. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit faf59e846f03b37c65996e58d045de8d64481283)
2012-08-27ENGR00221450 imx6 thermal: add sys_close() in cooling deviceRong Dian
add sys_close() to close opened file in cooling device Signed-off-by: Rong Dian <b38775@freescale.com>
2012-08-27ENGR00221197-2 Update gpu driver to check Soc temperatureLoren HUANG
-Update gpu driver to check the SoC temperature, if the thermal_hot flag is set by thermal driver. GPU3D clock will be slown down to the minimum value, the clock will be recovery when the flag is cleared by thermal driver. -This patch depends on ENGR00220848, without it, kernel build can't pass. Signed-off-by: Loren HUANG <b02279@freescale.com> Acked-by: Lily Zhang
2012-08-27ENGR00221197-1 imx6 thermal: clear thermal hot variable in cooling deviceRong Dian
clear thermal hot variable in cooling device when thermal temperature falls then to get out of THERMAL_TRIP_HOT state Signed-off-by: Rong Dian <b38775@freescale.com>
2012-08-27ENGR00221444 HDMI: video mode wrong when bootup without HDMI cableSandor Yu
Bootup Android without HDMI cable plugin, then plugin HDMI cable, video mode in /sys/class/graphics/fb0/mode not same as actually HDMI work video mode. The root cause is in video mode point to one of video mode in original video modelist, but the modelist will be updated when HDMI cable plug to new monitor. If HDMI original worked video mode can work on new monitor, the HDMI and framebuffer will not updated, so HDMI actually work mode not same as /sys/class/graphics/fb0/mode Updated fbi mode pointer even if video mode no changed in case moselist is updated, the issue will fixed. Signed-off-by: Sandor Yu <R01008@freescale.com>
2012-08-27ENGR00221445 ov5642: return error number when change camera modeYuxi Sun
return error number when set camera change mode fail, if not the driver may continue to setup the video processing with wrong parameter. Signed-off-by: Yuxi Sun <b36102@freescale.com>
2012-08-26ENGR00221161 [MX6SL]- Add audio bus freq mode support.Ranjani Vaidyanathan
Set DDR to 50MHz in low power audio playback. AHB/AXI are at 24MHz. Also fix correct usecount for PLL1 main clock. If not it causes issues when pll1_sw_clk's parent is changed. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-26ENGR00221440 MX6x-Fix race-condition in checking bus_freq variablesRanjani Vaidyanathan
Checking of the bus_freq variables and changing of the bus/ddr frequency should be done under one mutex. Else there is a race-condition that the variable changed just after it was checked. Also ensure that the bus freq is always increased before the cpu freq is set to anything other than the lowest setpoint. Else there is a possibility that the ARM is set to run from PLL1 at higher frequency when bus/DDR are still at 24MHz. This is dangerous since when system enters WAIT mode in low bus freq state, PLL1 is set to bypass when ARM is being sourced from it. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-26ENGR00221441 MX6SL - Update voltages based on the latest datasheet.Ranjani Vaidyanathan
Add a new working point table to MX6SL and set the voltages according to the latest datasheet. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-24ENGR00220796-3: imx6sl arm2/evk: Add platform_device for V4L2 supportRobby Cai
Add platform device for V4L2 support Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-24ENGR00220796-2: v4l2 imx6sl: Add V4L2 driver supportRobby Cai
Add V4L2 support -- driver part. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-24ENGR00220796-1: pxp: Add stride configuration for some pixel formatRobby Cai
Set correct PITCH (aka, stride) for AS, PS, Output buffer. This is needed for V4L2. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-24ENGR00219933 CS42888: abort delay powerdown if codec is onChen Liangjun
CS42888 driver own 2 codec_dai for ESAI and ASRC P2P use. Due to the delay power down mechanism, if a ASRC P2P stream is played right after a finish of ESAI stream playback, ASRC P2P stream would be stop. In this patch, do nothing in the delay powerdown flow if CS42888 codec is on. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-08-24ENGR00221203-2 IPU Device: replace BUG macro with error messageWayne Zou
Replace BUG macro with error message Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-08-24ENGR00221203-1 IPU Device: Avoid release resource twice when timeoutWayne Zou
Avoid release resource twice when timeout happen. Signed-off-by: Wayne Zou <b36644@freescale.com>
2012-08-24ENGR00221317-02 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
The Mx6 phy sometimes work abnormally after system suspend/resume if the 1V1 is off. So we should keep the 1V1 active during the system suspend if any USB host enabled. - Add stop_mode_config to 1 with refcount - Add mutex to protect the refcount and HW_ANADIG_ANA_MISC0 register - If stop_mode_config is set as 1, the otg vbus wakeup system will be supported Signed-off-by: make shi <b15407@freescale.com>
2012-08-24ENGR00221317-01 Mx6 USB host: set stop_mode_config when any USB host enabledmake shi
MSL headfile part change. Signed-off-by: make shi <b15407@freescale.com>
2012-08-23ENGR00221277 MX6DL/S - Set AXI clock to 270MHzRanjani Vaidyanathan
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2012-08-24ENGR00221177 ESAI ASRC: add mutex protection between ESAI and ASRC P2PChen Liangjun
ESAI playback and ASRC P2P playback use difference codec_dai while using the same codec. Thus they can't work together. In this patch, add mutual protection between ESAI playback and ASRC P2P playback. Signed-off-by: Chen Liangjun <b36089@freescale.com>
2012-08-23ENGR00221281 [MX6X] Fix BogoMIPS value is not correctNancy Chen
[MX6X] Fix BogoMIPS value is not correct Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
2012-08-24ENGR00221217 usb: device: fix usb_state incorrect problem after pc sends resumePeter Chen
At pc sends suspend/resume case, the udc_controller->usb_state should keep unchange during the suspend/resume process, at former code, the fsl_udc_resume set udc_controller->usb_state to USB_STATE_ATTACHED unconditionally. In fact, USB_STATE_ATTACHED stands for initial state and should be set when we try to run controller. Signed-off-by: Peter Chen <peter.chen@freescale.com>
2012-08-23ENGR00221131: imx6sl arm2/evk: add mma8450q accelerometer supportRobby Cai
mma8450q on E-INK DC3 boards, with i2c address 0x1c on I2C1. Signed-off-by: Robby Cai <R63905@freescale.com>
2012-08-23ENGR00221214 MX6Q/DL SabreSD: avoid pop-noise on audio padsGary Zhang
config audio pads to avoid pop-noise Signed-off-by: Gary Zhang <b13634@freescale.com>
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