Age | Commit message (Collapse) | Author |
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Sdma iapi start loading sdma script by write HSTART register as
memory. When instruction reorder and IRQ delay may let the next
synchronize operation wait forever.
We change it by using writel() to access sdma registers,
and introduce timeout to show this error.
HSTART and STOP_STAT contain bits that are reset by hardware.
So if we read-modify-write, we are in danger of setting a bit
after SDMA has cleared it.
The spec calls these registers "write-ones" register. So the
ARM can write a 1 to any bit, but does not need to worry about
clearing any bits that were previously set. SDMA hardware
keeps track of all bits that were set.
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>
Signed-off-by: Alan Tull <alan.tull@freescale.com>
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- Ensure that no updates are active when changing the FB info
- Fix criteria for evaluating whether any updates are active
Signed-off-by: Danny Nold <dannynold@freescale.com>
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1. Add discharge vbus when set vbus lower;
2. Due to unplug from HOST bring up suspend irq. add discharge in suspend irq.
3. Update port speed when port connect changed.
4. Add port speed verify in ep operation code.
Signed-off-by: Zhang Yan <b34916@freescale.com>
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When open mxc_iim twice, mxc_iim can't be close twice.
Signed-off-by: Terry Lv <r65388@freescale.com>
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mxc_iim: let mxc_iim work with dd and echo.
Signed-off-by: Terry Lv <r65388@freescale.com>
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If enabling DVFS core and enter suspend state, FEC resume was
failed due to wrong clock. This is because enter_lpapm_mode_mx51
function doesn't set low_bus_freq_mode flag after commit 30f6fc381.
It causes the system is in wrong low bus mode.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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MX53 loco&smd:preset suspend voltage in the latest stage because
Da9053 use the same register for preset and normal mode
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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CPU working point needs to be initialized based on the current CPU
frequency in start_dvfs() and should correspond with the correct entry
in the cpu_wp_auto table.
If its not initialized correctly, DVFS-CORE will fail when PLL-relock
results in a frequency that is not the same as set in the cpu_wp_auto table.
So fix it by finding the entry that closely matches the CPU frequency.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Error check of clk pointer should use IS_ERR instead of
ERR_PTR(ENOENT). Updated SCC2 and SAHARA drivers to use
this method for error checks as well as to propagate the
error code where applicable.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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mxc_iim can't be open twice.
The reason is that request_irq failed when open mxc_iim again.
So put request_irq function to probe function.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Restructure MX53 bus frequecy driver,
Add handlers for DDR3 boards,
MX53 DDR2 handlers not implemented in this patch
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Open usb clock before view usb debug file. avoid system hang when view
usb debug information in suspend state.
Signed-off-by: Zhang Yan <b34916@freescale.com>
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We used to force the framebuffer bpp to be default bpp
set by the user in the kernel boot up command line.
This patch fixes this issue. This patch also
gets TVE framebuffer bpp value from IPUv3 framebuffer.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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Only preset voltage for suspend to mem mode
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Problem fixed so remove warning message not to run OpenVG apps with X accel.
Signed-off-by: Dennis Wenzel <b21659@freescale.com>
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otg->host->is_b_host and otg->gadget->is_a_peripheral should be
updated at otg irq, as the host and device driver may use these two variables.
enable clk before request_irq
Signed-off-by: Peter Chen <peter.chen@freescale.com>
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Fix Mx28 L2Switch port learning not works issue.
Signed-off-by: Fan Zhicheng <r32736@freescale.com>
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Use arm_podf to switch cpu frequency when the pll_rate is
same. Remove pll settings for 400MHZ, 160MHZ since they
use arm_podf for cpu frequency change. For 1.2GHZ, 1GHZ,
800MHZ working point, relock pll is used. So pll settings
are kept.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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add 100ms delay after BT chip reset, make it work stable.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Refine pan display method.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Change ipu_check_buffer_busy to ipu_check_buffer_ready.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Change ipu_check_buffer_busy to ipu_check_buffer_ready.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Change to platform_device_register_simple().
Change check sysfs node to /sys/devices/platform/sii9022.0/cable_state.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Removed clk_disable call from ISR, and moved it to postprocess
function that is queued up for exection later. Also fixed debug
print that was referring to a non-existent struct member.
Signed-off-by: Anish Trivedi <anish@freescale.com>
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When bus is busy, for example vpu is working too, the timestamp is
possiblly not yet refreshed to memory by yamato when we get
GSL_INTR_YDX_CP_RING_BUFFER. For most cases, it will hit on first
loop cycle. So it don't effect performance.
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
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Current set_low_bus_freq codes enter low bus frequency automatically
if the CPU frequency is the lowest one. If only have one working
point, it enters low bus state in boot up phase. It causes mx53 RevA
board hang up in boot phase. And it also causes the bus frequency of
mx53 ard is reduced.
This patch doesn't allow to enter low bus state if only have 1 WP
Signed-off-by: Lily Zhang <r58066@freescale.com>
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add defconfig, remove gpio power key
fix some defconfig item miss
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Add da9053 power key config, add key up event
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Add max11801 touch screen driver for MX53_ARD.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Add MAXI max11801 resistance touch screen controller driver,
add a compile config of ts_lib calibration in driver, it is default disable.
This driver use Auto Mode and Aperture Mode.
Other max1180x driver could support in this driver further.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Make sure only DA9053 irq configured as wakeup source for mx53 smd &loco
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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This patch checks slave device is attached before calling
any internal ioctrl to avoid NULL pointer de-referencing.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch adds TVDAC regulator for TVE platform data.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch correct TVDAC regulator voltage value to
be 2.75V.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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add performance monitor driver.
sample:
cd /sys/devices/platform/mxs-perfmon.0/
'echo 1 > MIDn-xxx' to enable monitor this channel
n: channel number; xxx: name of channel (PXP, LCD...)
you can enable the multiple channels you want to
monitor respectively using this command.
use following command to check the channel is enabled
'cat MIDn-xxx'
1: enable; 0: disable
'echo read > Monitor' to monitor all read activities
'echo start > Monitor' to start monitoring
'echo fetch > Monitor' to get a snapshot of monitor statistics.
'cat xxx_Count' to show the statistics.
xxx: name of statistics, (Data, Transfer, Latency...)
'echo clear > Monitor' to clear snapshot of monitor statistics.
'echo stop > Monitor' to stop monitoring
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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enable performance monitor driver for system loading analysis
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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enable performance monitor driver for system loading analysis
Signed-off-by: Tony Lin <tony.lin@freescale.com>
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1) Enable WiFi power during system boot up or WiFi card can not
be detected.
2) Remove BT Power on/off control in RFKILL function because bt/wifi
are sharing one regulator and has conflicts on power control.
Signed-off-by: Aisheng.Dong <b29396@freescale.com>
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EV_MSC will ignore by some system, so change this device to a EV_KEY
device.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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Change key order per MX53 SMD board design.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
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This patch adds Seiko WVGA LCD panel support.
Note that you need to populate D4 on the LCD board.
You need to use this fb videomode:
video=mxcdi0fb:RGB24,SEIKO-WVGA
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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This patch changes to use OV3640 defaultly.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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add cea ext block parser.
it provide more video modes and the info of device HDMI compatible.
Signed-off-by: Jason Chen <b02280@freescale.com>
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add cea ext block parser.
it provide more video modes and the info of device HDMI compatible.
Signed-off-by: Jason Chen <b02280@freescale.com>
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The parent clk of asrc serial clk is PLL4. After PLL4 clk is
changed as 455MHZ in U-Boot, asrc serial clk is not right.
So the patch uses round_rate to set asrc serial clk and make
it pass clk rate check.
This patch also moves asrc serial clk set from board file to
clock file.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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mx50rdp, mx51bbg, mx53evk:
Add get keypad press status callback and desired send key value
to the platform data.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Add get keypad press status callback and desired send key value
to the platform data.
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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fb cmdline option bpp= should pass the default bpp to fb driver, for tve etc
case, it will set_var by itself, which var->bits_per_pixel = 0,
the mxcfb_check_var will then fix it to 16. It's not correct
when we need set bpp to other value.
Signed-off-by: Jason Chen <b02280@freescale.com>
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Add mx53 smd&loco suspend via i2c command
Only a maximu 30ms delay before da9053 enter suspend, thus
the command is sent out at the latest stage of system suspend
operation when all other drivers already suspended and irq disabled.
A standalone polling-mode i2c interface is therefor deployed for the suspend
command operations.
In current solution, mx53 fails to resume from 1GHZ working poing when reduce
VDD &VCC to stop mode level. Thus a workaround is added to set mx53 working
point to 400MHZ before suspend and restore to previous working point after
it resume back.
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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Add da9053 driver code support for suspend
Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
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