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2014-11-19ARM: dts: imx6: add pm_power_off support for i.mx6 chipsimx-dt-3.19Robin Gong
All chips of i.mx6 can be powered off by programming SNVS. For example : On i.mx6q-sabresd board, PMIC_ON_REQ connect with external pmic ON/OFF pin, that will cause the whole PMIC powered off except VSNVS. And system can restart once PMIC_ON_REQ goes high by push POWRER key. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf-colibri: add USB regulatorsStefan Agner
Add structure of USB supply logic. The USB hosts power enable regulator is needed to control VBUS supply on the Colibri carrier board. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6: phyFLEX: Add CAN supportChristian Hemp
Add CAN support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01). Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6: phyFLEX: Add PCIeChristian Hemp
Add PCIe support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01). Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6: phyFLEX: Set correct interrupt for pmicChristian Hemp
The PMIC interrupt was changed from modul revision 1 to 2. Revision 1 was declared as a prototype and is not in series by any customers. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6: phyFLEX: Enable gpmi in module fileChristian Hemp
The nand is on the module (PFL-A-02) and not on the baseboard (PBA-B-01). Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6: phyFLEX: set nodes in alphabetical orderChristian Hemp
The gmpi and fec node were not in alphabatical order. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf-colibri-eval-v3.dts: Enable ST-M41T0M6 RTCBhuvanchandra DV
ST-M41T0M6 is available on Colibri carrier boards. Hence enable M41T0M6 RTC. Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf-colibri: Add I2C supportBhuvanchandra DV
Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6qdl: Enable CODA960 VPUPhilipp Zabel
This patch adds links to the on-chip SRAM and reset controller nodes and switches the interrupts. Make the BIT processor interrupt, which exists on all variants, the first one. The JPEG unit interrupt, which does not exist on i.MX27 and i.MX5 thus is an optional second interrupt. Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to load separate firmware images for some reason. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6q-tbs2910: Remove unneeded 'fsl,mode' propertyFabio Estevam
imx6q-tbs2910 board uses sgtl5000 codec and the machine file (imx-sgtl5000) already sets SSI in slave mode and codec in master mode, so there is no need for having this property. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf610: enable USB misc/phy nodes where necessaryStefan Agner
Since restructuring of the device tree files, the USB misc/phy nodes are disabled by default. Hence we need to enable those explicitly when USB is used. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf610: use new GPIO supportStefan Agner
Use GPIO support by adding SD card detection configuration and GPIO pinmux for Colibri's standard GPIO pins. Attach the GPIO pins to the iomuxc node to get the GPIO pin settings applied. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: pbab01: enable I2S audio on phyFLEX-i.MX6 boardsDmitry Lavnikevich
Audio on phyFLEX boards is presented by tlv320aic3007 codec connected over SSI interface. Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02Dmitry Lavnikevich
Since pins and frequency are specific to module (pfla02), not base board (pbab02), it is better to be initialized in corresponding dts file. This patch fixes i2c2, i2c3 pin configuration which caused messages: imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c2grp imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c3grp imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c2grp imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c3grp Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf500-colibri: add Colibri VF50 supportStefan Agner
Add Colibri VF50 device tree files vf500-colibri.dtsi and vf500-colibri-eval-v3.dts, in line with the Colibri VF61 device tree files. However, to minimize dupplication we also add vf-colibri.dtsi and vf-colibri-eval-v3.dtsi which contain the common device tree nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf610: create generic base device treesStefan Agner
This adds more generic base device trees for Vybrid SoCs. There are three series of Vybrid SoC commonly available: - VF3xx series: single core, Cortex-A5 without external memory - VF5xx series: single core, Cortex-A5 - VF6xx series: dual core, Cortex-A5/Cortex-M4 The second digit represents the presents of a L2 cache (VFx1x). The VF3xx series are not suitable for Linux especially since the internal memory is quite small (1.5MiB). The VF500 is essentially the base SoC, with only one core and without L1 cache. The VF610 is a superset of the VF500, hence vf500.dtsi is then included and enhanced by vf610.dtsi. There is no board using VF510 or VF600 currently, but, if needed, they can be added easily. The Linux kernel can also run on the Cortex-M4 CPU of Vybrid using !MMU support. This patchset creates a device tree structure which allows to share peripherals nodes for a VF6xx Cortex-M4 device tree too. The two CPU types have different views of the system: Foremost they are using different interrupt controllers, but also the memory map is slightly different. The base device tree vfxxx.dtsi allows to create SoC and board level device trees supporting the Cortex-M4 while reusing the shared peripherals nodes. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: vf610: assign oscillator to clock moduleStefan Agner
The clock controller module (CCM) has several clock inputs, which are connected to external crystal oscillators. To reflect this, assign these fixed clocks to the CCM node directly. This especially resolves initialization order dependencies we had with the earlier initialization code: When resolving of the fixed clocks failed in clk-vf610, the code created fixed clocks with a rate of 0. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19dt-bindings: arm: add Freescale LS1021A SoC device tree bindingJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: Add initial LS1021A TWR board dts supportJingchang Lu
The LS1021A TWR is a low cost, high-performance evaluation, development and test platform supporting the LS1021A processor. It is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. For more detail information about the LS1021A TWR board, please refer to LS1021A QorIQ Tower System Reference Manual. Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: Add initial LS1021A QDS board dts supportJingchang Lu
The LS1021A QorIQ development system (QDS) is a high-performance computing evaluation, development and test platform supporting the LS1021A processor. The LS1021A QDS is optimized to support the high-bandwidth DDR3LP/DDR4 memory and a full complement of high-speed SerDes ports. For more detail information about the LS1021AQDS, please refer to the QorIQ LS1021A Development System Reference Manual. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: Add SoC level device tree support for LS1021AJingchang Lu
This add Freescale QorIQ LS1021A SoC device tree support. The QorIQ LS1021A processor incorporates dual ARM Cortex-A7 cores, providing virtualization support, advanced security features and the broadest array of high-speed interconnects and optimized peripheral features. The LS1021A SoC shares IPs with i.MX, Vybrid and PowerPC platform. For the detail information about Freescale QorIQ LS1021A SoC, please refer to the QorIQ LS1021A Reference Manual. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6dl: add alias for I2C4 busVladimir Zapolskiy
On registration I2C bus drivers attemp to get ids from device tree aliases, add a missing alias for I2C4 found on iMX6 DualLite/Solo. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: add initial support for TBS2910 Matrix ARM mini PCSoeren Moch
TBS2910 is a i.MX6Q based board. For additional details refer to http://www.tbsdtv.com/products/tbs2910-matrix-arm-mini-pc.html Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19devicetree: bindings: Add vendor prefix for TBS TechnologiesSoeren Moch
TBS Technologies is a company which specializes in developing, producing and marketing of digital TV tuner cards for PCs. for additional details refer to http://www.tbsdtv.com/about-us.html Signed-off-by: Soeren Moch <smoch@web.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx6x: Add enet2 support for imx6sx-sdb boardFugang Duan
Add enet2 support for imx6sx-sdb board, and add the "fsl,imx6q-fec" compatible for fec2 node to be compatible with the old version. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: dts: imx53: add cpufreq-dt supportLucas Stach
Add all required properties for the cpufreq-dt driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: vf610-colibri: Add ADC supportSanchayan Maity
Enable ADC support for Colibri VF61 modules Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: vf610-colibri: Add backlight supportBhuvanchandra DV
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: vf610-colibri: Add PWM supportBhuvanchandra DV
The Colibri standard defines four pins as PWM outputs, two of them (PWM A and C) are routed to FTM instance 0 and the other two (PWM B and D) are routed to FTM instance 1. Hence enable both FTM instances for the Colibri module and mux the four pins accordingly. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: vf610: Add PWM second instanceBhuvanchandra DV
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: vf610: Add ARM Global TimerStefan Agner
Add Global Timer support which is part of the private peripherals of the Cortex-A5 processor. This Global Timer is compatible with the Cortex-A9 implementation. It's a 64-bit timer and is clocked by the peripheral clock, which is typically 133 or 166MHz on Vybrid. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: imx51: Improve SSI clocks descriptionFabio Estevam
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode. Add the extra 'baud' clock so that we can have SSI functional in master mode. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: dts: imx53: Improve SSI clocks descriptionFabio Estevam
SSI block has 'ipg' clock for internal peripheral access and also 'baud' clock for generating bit clock when SSI operates in master mode. Add the extra 'baud' clock so that we can have SSI functional in master mode. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: configs: imx_v6_v7_defconfig: add power off driverimx-soc-3.19Robin Gong
Add power off driver in config file. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19power: reset: imx-snvs-poweroff: add power off driver for i.mx6Robin Gong
This driver register pm_power_off with snvs power off function. If your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use other pin to do, please disable the driver in dts, otherwise, your pm_power_off maybe overwrote by this driver. Signed-off-by: Robin Gong <b38343@freescale.com> Acked-By: Sebastian Reichel <sre@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021AArnd Bergmann
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which is originally symbol used for the PowerPC based platforms and guards lots of code that does not build on ARM. This breaks allmodconfig, so let's remove it for now, until either all those drivers are fixed or they use a dependency on IMX instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx_v6_v7_defconfig: Select thermal related driversFabio Estevam
Allow the reading of temperature in userspace via: cat /sys/class/thermal/thermal_zone0/temp Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx_v6_v7_defconfig: enable DS1307 rtc and gpio fan by defaultSoeren Moch
Used on TBS2910 board. Signed-off-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx_v6_v7_defconfig: enable tlv320aic3x audio codec by defaultDmitry Lavnikevich
Used on Phytec PBAB01 board. Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx: clk-vf610: get input clocks from assigned clocksStefan Agner
With the clock assignment device tree changes, the clocks get initialized properly but the search for those clocks fails with errors: [ 0.000000] i.MX clk 4: register failed with -17 [ 0.000000] i.MX clk 5: register failed with -17 This is because the module can't find those clocks anymore, and tries to initialize fixed clocks with the same name. Get the clock modules input clocks from the assigned clocks by default by using of_clk_get_by_name(). If this function returns not a valid clock, fall back to the old behaviour and search the input clock from the device tree's /clocks/$name node. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu
Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx: Add initial support for Freescale LS1021AJingchang Lu
The LS1021A SoC is a dual-core Cortex-A7 based processor, this adds the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx53: add cpufreq supportLucas Stach
Instanciate device for the generic cpufreq-dt driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-19ARM: imx53: clk: add ARM clockLucas Stach
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: imx: add CPU clock typeLucas Stach
This implements a virtual clock used to abstract away all the steps needed in order to change the ARM clock, so we don't have to push all this clock handling into the cpufreq driver. While it will be used for i.MX53 at first it is generic enough to be used on i.MX6 later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: imx5: add step clock, used when reprogramming PLL1Lucas Stach
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: imx: add enet init for i.mx6sxFugang Duan
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: imx6sx: add imx6sx iomux-gpr field defineFugang Duan
Add imx6sx iomux-gpr register field define in "imx6q-iomuxc-gpr.h" header file, which is not fully define all iomux-gpr registers and fields, only align with freescale internal tree related GPR macro define. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-19ARM: vf610: Add ARM Global Timer clocksource optionStefan Agner
Add the ARM Global Timer as clocksource/scheduler clock option and use it as default scheduler clock. This leaves the PIT timer for other users e.g. the secondary Cortex-M4 core. Also, the Global Timer has double the precission (running at pheripheral clock compared to IPG clock) and a 64-bit incrementing counter register. We still keep the PIT timer as an secondary option in case the ARM Global Timer is not available. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>