diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi | 226 |
1 files changed, 226 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi new file mode 100644 index 000000000000..984e40cd5ef3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi @@ -0,0 +1,226 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This dtsi is used by dom0 mainly for passthrough devices to domu. + */ +/ { + /delete-node/ thermal-zones; + + /delete-node/ wu; + + edma00: dma-controller0@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx"; + status = "okay"; + }; + + edma01: dma-controller1@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; + status = "okay"; + }; + + edma02: dma-controller2@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx"; + status = "okay"; + }; + + edma03: dma-controller3@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx"; + status = "okay"; + }; + + edma04: dma-controller4@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <2>; + interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx"; + status = "okay"; + }; + + usbotg1_lpcg: usbotg1_lpcg@5b270000 { + compatible = "fsl,imx8qm-usbotg1-lpcg"; + reg = <0x0 0x5b270000 0x0 0x10000>; + }; + + sdhc1_lpcg: sdhc1_lpcg@5b200000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5b200000 0x0 0x10000>; + }; + + lpuart1_lpcg: lpcg@5a470000 { + compatible = "fsl,imx8qm-lpuart-lpcg"; + reg = <0x0 0x5a470000 0x0 0x10000>; + }; + + di_lvds0_lpcg: lpcg@56243000 { + compatible = "fsl,imx8qm-di-lvds0-lpcg"; + reg = <0x0 0x56243000 0x0 0x1000>; + }; + + di_lvds1_lpcg: lpcg@57243000 { + compatible = "fsl,imx8qm-di-lvds1-lpcg"; + reg = <0x0 0x57243000 0x0 0x1000>; + }; + + dc_0_lpcg: lpcg@56010000 { + compatible = "fsl,imx8qm-dc0-lpcg"; + reg = <0x0 0x56010000 0x0 0x10000>; + }; + + dc_1_lpcg: lpcg@57010000 { + compatible = "fsl,imx8qm-dc1-lpcg"; + reg = <0x0 0x57010000 0x0 0x10000>; + }; +}; + +/delete-node/ &edma0; + +&mu { + interrupt-parent = <&gic>; +}; + +&flexcan1 { + interrupt-parent = <&gic>; +}; + +&flexcan2 { + interrupt-parent = <&gic>; +}; + +&flexcan3 { + interrupt-parent = <&gic>; +}; + +&lpuart0 { + interrupt-parent = <&gic>; +}; + +&lpuart1 { + interrupt-parent = <&gic>; + dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; +}; + +&lpuart2 { + interrupt-parent = <&gic>; + dmas = <&edma02 17 0 0>, <&edma02 16 0 1>; +}; + +&lpuart3 { + interrupt-parent = <&gic>; + dmas = <&edma03 19 0 0>, <&edma03 18 0 1>; +}; + +&lpuart4 { + interrupt-parent = <&gic>; + dmas = <&edma04 21 0 0>, <&edma04 20 0 1>; +}; + +&usdhc1 { + /delete-property/ iommus; +}; + +&usdhc2 { + /delete-property/ iommus; +}; + +&usdhc3 { + /delete-property/ iommus; +}; + +&fec1 { + interrupt-parent = <&gic>; + /delete-property/ iommus; +}; + +&fec2 { + interrupt-parent = <&gic>; + /delete-property/ iommus; +}; + +&sata { + /delete-property/ iommus; +}; + +&usbotg1 { + interrupt-parent = <&gic>; +}; + +&usbh1 { + interrupt-parent = <&gic>; +}; + +&usbotg3 { + interrupt-parent = <&gic>; +}; + +&smmu { + /* xen only supports legacy bindings for now */ + #iommu-cells = <0>; +}; + +&dpu1 { + fsl,sc_rsrc_id = <SC_R_DC_0_BLIT0>, + <SC_R_DC_0_BLIT1>, + <SC_R_DC_0_BLIT2>, + <SC_R_DC_0_BLIT_OUT>, + <SC_R_DC_0_WARP>, + <SC_R_DC_0_VIDEO0>, + <SC_R_DC_0_VIDEO1>, + <SC_R_DC_0_FRAC0>, + <SC_R_DC_0>; +}; + +&dpu2 { + fsl,sc_rsrc_id = <SC_R_DC_1_BLIT0>, + <SC_R_DC_1_BLIT1>, + <SC_R_DC_1_BLIT2>, + <SC_R_DC_1_BLIT_OUT>, + <SC_R_DC_1_WARP>, + <SC_R_DC_1_VIDEO0>, + <SC_R_DC_1_VIDEO1>, + <SC_R_DC_1_FRAC0>, + <SC_R_DC_1>; +}; |