diff options
Diffstat (limited to 'arch/arm/mach-stmp378x/include/mach/regs-spdif.h')
| -rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-spdif.h | 198 |
1 files changed, 176 insertions, 22 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h index 801539848c28..54cee6519496 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h @@ -1,7 +1,7 @@ /* - * stmp378x: SPDIF register definitions + * STMP SPDIF Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,33 +17,187 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) -#define REGS_SPDIF_PHYS 0x80054000 -#define REGS_SPDIF_SIZE 0x2000 -#define HW_SPDIF_CTRL 0x0 -#define BM_SPDIF_CTRL_RUN 0x00000001 -#define BP_SPDIF_CTRL_RUN 0 -#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 -#define BM_SPDIF_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___SPDIF_H +#define __ARCH_ARM___SPDIF_H 1 + +#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) +#define REGS_SPDIF_PHYS (0x80054000) +#define REGS_SPDIF_SIZE 0x00002000 + +#define HW_SPDIF_CTRL (0x00000000) +#define HW_SPDIF_CTRL_SET (0x00000004) +#define HW_SPDIF_CTRL_CLR (0x00000008) +#define HW_SPDIF_CTRL_TOG (0x0000000c) +#define HW_SPDIF_CTRL_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL) +#define HW_SPDIF_CTRL_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET) +#define HW_SPDIF_CTRL_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR) +#define HW_SPDIF_CTRL_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL_TOG) + #define BM_SPDIF_CTRL_SFTRST 0x80000000 +#define BM_SPDIF_CTRL_CLKGATE 0x40000000 +#define BP_SPDIF_CTRL_RSRVD1 21 +#define BM_SPDIF_CTRL_RSRVD1 0x3FE00000 +#define BF_SPDIF_CTRL_RSRVD1(v) \ + (((v) << 21) & BM_SPDIF_CTRL_RSRVD1) +#define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_SPDIF_CTRL_DMAWAIT_COUNT) +#define BP_SPDIF_CTRL_RSRVD0 6 +#define BM_SPDIF_CTRL_RSRVD0 0x0000FFC0 +#define BF_SPDIF_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_SPDIF_CTRL_RSRVD0) +#define BM_SPDIF_CTRL_WAIT_END_XFER 0x00000020 +#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 +#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_SPDIF_CTRL_RUN 0x00000001 -#define HW_SPDIF_STAT 0x10 +#define HW_SPDIF_STAT (0x00000010) +#define HW_SPDIF_STAT_SET (0x00000014) +#define HW_SPDIF_STAT_CLR (0x00000018) +#define HW_SPDIF_STAT_TOG (0x0000001c) +#define HW_SPDIF_STAT_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT) +#define HW_SPDIF_STAT_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT_SET) +#define HW_SPDIF_STAT_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT_CLR) +#define HW_SPDIF_STAT_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT_TOG) -#define HW_SPDIF_FRAMECTRL 0x20 +#define BM_SPDIF_STAT_PRESENT 0x80000000 +#define BP_SPDIF_STAT_RSRVD1 1 +#define BM_SPDIF_STAT_RSRVD1 0x7FFFFFFE +#define BF_SPDIF_STAT_RSRVD1(v) \ + (((v) << 1) & BM_SPDIF_STAT_RSRVD1) +#define BM_SPDIF_STAT_END_XFER 0x00000001 -#define HW_SPDIF_SRR 0x30 -#define BM_SPDIF_SRR_RATE 0x000FFFFF -#define BP_SPDIF_SRR_RATE 0 -#define BM_SPDIF_SRR_BASEMULT 0x70000000 +#define HW_SPDIF_FRAMECTRL (0x00000020) +#define HW_SPDIF_FRAMECTRL_SET (0x00000024) +#define HW_SPDIF_FRAMECTRL_CLR (0x00000028) +#define HW_SPDIF_FRAMECTRL_TOG (0x0000002c) +#define HW_SPDIF_FRAMECTRL_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL) +#define HW_SPDIF_FRAMECTRL_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_SET) +#define HW_SPDIF_FRAMECTRL_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_CLR) +#define HW_SPDIF_FRAMECTRL_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_TOG) + +#define BP_SPDIF_FRAMECTRL_RSRVD2 18 +#define BM_SPDIF_FRAMECTRL_RSRVD2 0xFFFC0000 +#define BF_SPDIF_FRAMECTRL_RSRVD2(v) \ + (((v) << 18) & BM_SPDIF_FRAMECTRL_RSRVD2) +#define BM_SPDIF_FRAMECTRL_V_CONFIG 0x00020000 +#define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x00010000 +#define BM_SPDIF_FRAMECTRL_RSRVD1 0x00008000 +#define BM_SPDIF_FRAMECTRL_USER_DATA 0x00004000 +#define BM_SPDIF_FRAMECTRL_V 0x00002000 +#define BM_SPDIF_FRAMECTRL_L 0x00001000 +#define BM_SPDIF_FRAMECTRL_RSRVD0 0x00000800 +#define BP_SPDIF_FRAMECTRL_CC 4 +#define BM_SPDIF_FRAMECTRL_CC 0x000007F0 +#define BF_SPDIF_FRAMECTRL_CC(v) \ + (((v) << 4) & BM_SPDIF_FRAMECTRL_CC) +#define BM_SPDIF_FRAMECTRL_PRE 0x00000008 +#define BM_SPDIF_FRAMECTRL_COPY 0x00000004 +#define BM_SPDIF_FRAMECTRL_AUDIO 0x00000002 +#define BM_SPDIF_FRAMECTRL_PRO 0x00000001 + +#define HW_SPDIF_SRR (0x00000030) +#define HW_SPDIF_SRR_SET (0x00000034) +#define HW_SPDIF_SRR_CLR (0x00000038) +#define HW_SPDIF_SRR_TOG (0x0000003c) +#define HW_SPDIF_SRR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR) +#define HW_SPDIF_SRR_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR_SET) +#define HW_SPDIF_SRR_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR_CLR) +#define HW_SPDIF_SRR_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR_TOG) + +#define BM_SPDIF_SRR_RSRVD1 0x80000000 #define BP_SPDIF_SRR_BASEMULT 28 +#define BM_SPDIF_SRR_BASEMULT 0x70000000 +#define BF_SPDIF_SRR_BASEMULT(v) \ + (((v) << 28) & BM_SPDIF_SRR_BASEMULT) +#define BP_SPDIF_SRR_RSRVD0 20 +#define BM_SPDIF_SRR_RSRVD0 0x0FF00000 +#define BF_SPDIF_SRR_RSRVD0(v) \ + (((v) << 20) & BM_SPDIF_SRR_RSRVD0) +#define BP_SPDIF_SRR_RATE 0 +#define BM_SPDIF_SRR_RATE 0x000FFFFF +#define BF_SPDIF_SRR_RATE(v) \ + (((v) << 0) & BM_SPDIF_SRR_RATE) + +#define HW_SPDIF_DEBUG (0x00000040) +#define HW_SPDIF_DEBUG_SET (0x00000044) +#define HW_SPDIF_DEBUG_CLR (0x00000048) +#define HW_SPDIF_DEBUG_TOG (0x0000004c) +#define HW_SPDIF_DEBUG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG) +#define HW_SPDIF_DEBUG_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG_SET) +#define HW_SPDIF_DEBUG_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG_CLR) +#define HW_SPDIF_DEBUG_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG_TOG) + +#define BP_SPDIF_DEBUG_RSRVD1 2 +#define BM_SPDIF_DEBUG_RSRVD1 0xFFFFFFFC +#define BF_SPDIF_DEBUG_RSRVD1(v) \ + (((v) << 2) & BM_SPDIF_DEBUG_RSRVD1) +#define BM_SPDIF_DEBUG_DMA_PREQ 0x00000002 +#define BM_SPDIF_DEBUG_FIFO_STATUS 0x00000001 + +#define HW_SPDIF_DATA (0x00000050) +#define HW_SPDIF_DATA_SET (0x00000054) +#define HW_SPDIF_DATA_CLR (0x00000058) +#define HW_SPDIF_DATA_TOG (0x0000005c) +#define HW_SPDIF_DATA_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA) +#define HW_SPDIF_DATA_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA_SET) +#define HW_SPDIF_DATA_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA_CLR) +#define HW_SPDIF_DATA_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA_TOG) -#define HW_SPDIF_DEBUG 0x40 +#define BP_SPDIF_DATA_HIGH 16 +#define BM_SPDIF_DATA_HIGH 0xFFFF0000 +#define BF_SPDIF_DATA_HIGH(v) \ + (((v) << 16) & BM_SPDIF_DATA_HIGH) +#define BP_SPDIF_DATA_LOW 0 +#define BM_SPDIF_DATA_LOW 0x0000FFFF +#define BF_SPDIF_DATA_LOW(v) \ + (((v) << 0) & BM_SPDIF_DATA_LOW) -#define HW_SPDIF_DATA 0x50 +#define HW_SPDIF_VERSION (0x00000060) +#define HW_SPDIF_VERSION_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_VERSION) -#define HW_SPDIF_VERSION 0x60 +#define BP_SPDIF_VERSION_MAJOR 24 +#define BM_SPDIF_VERSION_MAJOR 0xFF000000 +#define BF_SPDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SPDIF_VERSION_MAJOR) +#define BP_SPDIF_VERSION_MINOR 16 +#define BM_SPDIF_VERSION_MINOR 0x00FF0000 +#define BF_SPDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_SPDIF_VERSION_MINOR) +#define BP_SPDIF_VERSION_STEP 0 +#define BM_SPDIF_VERSION_STEP 0x0000FFFF +#define BF_SPDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_SPDIF_VERSION_STEP) +#endif /* __ARCH_ARM___SPDIF_H */ |