diff options
5 files changed, 57 insertions, 10 deletions
diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt index b8aaf317ed0e..1c7f8a3e10cf 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt @@ -362,7 +362,7 @@ Example nvidia,out-type = <TEGRA_DC_OUT_HDMI>; nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH TEGRA_DC_OUT_HOTPLUG_WAKE_LP0>; nvidia,out-parent-clk = "pll_d2"; - nvidia,out-max-pixclk = <297000>; + nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt index 83cfc2df95a0..5fd7b27fdedb 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt @@ -32,6 +32,7 @@ NVIDIA TEGRA114 High Definition Multimedia Interface Required properties: - name: Can be arbitrary, but each sibling node should have unique name. + - version: tmds configuration version. two tuples items needs to be written.: <major minor> - pclk: pixel clk required in tmds table for each mode. - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM. - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM. @@ -41,6 +42,8 @@ NVIDIA TEGRA114 High Definition Multimedia Interface See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM. - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane. See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM. + - pad-ctls0-mask: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register and mask. + - pad-ctls0-setting: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register or mask. Example host1x { diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt index 3a081a29cc87..ca1f5e733bac 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt @@ -362,7 +362,7 @@ Example nvidia,out-type = <TEGRA_DC_OUT_HDMI>; nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH TEGRA_DC_OUT_HOTPLUG_WAKE_LP0>; nvidia,out-parent-clk = "pll_d2"; - nvidia,out-max-pixclk = <297000>; + nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt index 9a0ccc2f5e6f..8613c36a9be3 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt @@ -32,6 +32,7 @@ NVIDIA TEGRA124 High Definition Multimedia Interface Required properties: - name: Can be arbitrary, but each sibling node should have unique name. + - version: tmds configuration version. two tuples items needs to be written.: <major minor> - pclk: pixel clk required in tmds table for each mode. - pll0: See HDMI_NV_PDISP_SOR_PLL0_0 in Tegra TRM. - pll1: See HDMI_NV_PDISP_SOR_PLL1_0 in Tegra TRM. @@ -41,6 +42,8 @@ NVIDIA TEGRA124 High Definition Multimedia Interface See HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT_0 in Tegra TRM. - peak-current: New pad controls for 28nm macro TMDS_X4_HP 8 bits per lane. See HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT_0 in Tegra TRM. + - pad-ctls0-mask: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register and mask. + - pad-ctls0-setting: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register or mask. Example host1x { diff --git a/drivers/video/tegra/dc/of_dc.c b/drivers/video/tegra/dc/of_dc.c index f126ad10e351..7785d58502b3 100644 --- a/drivers/video/tegra/dc/of_dc.c +++ b/drivers/video/tegra/dc/of_dc.c @@ -188,9 +188,38 @@ static int parse_tmds(struct device_node *np, u8 *addr) { u32 temp; + int i = 0; + u32 major = 0; + u32 minor = 0; + struct property *prop; + const __be32 *p; + u32 u; struct tmds_config *tmds_cfg_addr; tmds_cfg_addr = (struct tmds_config *)addr; + of_property_for_each_u32(np, "version", prop, p, u) + i++; + + if (i == 2) { /* major version, minor version */ + i = 0; + of_property_for_each_u32(np, + "version", prop, p, u) { + i++; + if (i == 1) + major = u; + else + minor = u; + } + tmds_cfg_addr->version = MKDEV(major, minor); + OF_DC_LOG("tmds version 0x%x\n", + tmds_cfg_addr->version); + } else if (i == 0) { + OF_DC_LOG("there's no tmds conf version.\n"); + } else { + OF_DC_LOG("need to have major, minor version\n"); + goto parse_tmds_fail; + } + if (!of_property_read_u32(np, "pclk", &temp)) { tmds_cfg_addr->pclk = (int)temp; OF_DC_LOG("tmds pclk %d\n", temp); @@ -199,31 +228,43 @@ static int parse_tmds(struct device_node *np, } if (!of_property_read_u32(np, "pll0", &temp)) { tmds_cfg_addr->pll0 = (u32)temp; - OF_DC_LOG("tmds pll0 %d\n", temp); + OF_DC_LOG("tmds pll0 0x%x\n", temp); } else { goto parse_tmds_fail; } if (!of_property_read_u32(np, "pll1", &temp)) { tmds_cfg_addr->pll1 = (u32)temp; - OF_DC_LOG("tmds pll1 %d\n", temp); + OF_DC_LOG("tmds pll1 0x%x\n", temp); } else { goto parse_tmds_fail; } if (!of_property_read_u32(np, "pe-current", &temp)) { tmds_cfg_addr->pe_current = (u32)temp; - OF_DC_LOG("tmds pe-current %d\n", temp); + OF_DC_LOG("tmds pe-current 0x%x\n", temp); } else { goto parse_tmds_fail; } if (!of_property_read_u32(np, "drive-current", &temp)) { tmds_cfg_addr->drive_current = (u32)temp; - OF_DC_LOG("tmds drive-current %d\n", temp); + OF_DC_LOG("tmds drive-current 0x%x\n", temp); } else { goto parse_tmds_fail; } if (!of_property_read_u32(np, "peak-current", &temp)) { tmds_cfg_addr->peak_current = (u32)temp; - OF_DC_LOG("tmds peak-current %d\n", temp); + OF_DC_LOG("tmds peak-current 0x%x\n", temp); + } else { + goto parse_tmds_fail; + } + if (!of_property_read_u32(np, "pad-ctls0-mask", &temp)) { + tmds_cfg_addr->pad_ctls0_mask = (u32)temp; + OF_DC_LOG("tmds pad_ctls0_mask 0x%x\n", temp); + } else { + goto parse_tmds_fail; + } + if (!of_property_read_u32(np, "pad-ctls0-setting", &temp)) { + tmds_cfg_addr->pad_ctls0_setting = (u32)temp; + OF_DC_LOG("tmds pad_ctls0_setting 0x%x\n", temp); } else { goto parse_tmds_fail; } @@ -310,9 +351,9 @@ static int parse_dc_default_out(struct platform_device *ndev, default_out->hotplug_gpio = hotplug_gpio; } if (!of_property_read_u32(np, "nvidia,out-max-pixclk", &temp)) { - default_out->max_pixclock = (unsigned) KHZ2PICOS(temp); - OF_DC_LOG("khz %d => out_dcc %d in picos unit\n", - temp, default_out->max_pixclock); + default_out->max_pixclock = (unsigned)temp; + OF_DC_LOG("%u max_pixclock in pico second unit\n", + default_out->max_pixclock); } of_property_for_each_u32(np, "nvidia,out-flags", prop, p, u) { |