diff options
| -rw-r--r-- | Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt | 352 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt | 355 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt | 193 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt | 353 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt | 355 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt | 193 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/dc.c | 1 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/of_dc.c | 574 | ||||
| -rw-r--r-- | include/dt-bindings/display/tegra-panel.h | 8 |
9 files changed, 1332 insertions, 1052 deletions
diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt index 1c7f8a3e10cf..1e1330b89b00 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dc.txt @@ -17,360 +17,48 @@ NVIDIA Tegra114 Display Controller - nvidia,cmu-enable: Toggle switch for color management unit. - nvidia,low-v-win: If low_v_win is set, we can lower vdd_core when that windows is the only one active. - - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage, - HDMI_AVDD. - - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply. - - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source. - - - Child nodes represent node of modes, output settings, framebuffer data, - smart dimmer settings, color management unit settings, dsi output device settings. - -1.A) NVIDIA Display Controller Modes - This must be contained in dc parent node. This contains supported modes. - - Required properties: - - name: Should be "display-timings" - - - Child nodes represent modes. Several modes can be prepared. - -1.A.i) NVIDIA Display Controller Mode timing - This must be contained in display-timings parent node. This contains mode settings, including - display timings. For hdmi out-type case, display-timings properties are only valid in case of - hdmi fb console mode. - - Required properties: - - name: Can be arbitrary, but each sibling node should have unique name. - - hactive, vactive: display resolution. - - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters - in pixels. - - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in - lines. - - clock-frequency: display clock in Hz. - - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC - with respect to H reference point. - - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC - with respect to V reference point. - -1.B) NVIDIA Display Controller Default Output Settings - This must be contained in dc parent node. This is default output settings. - - Required properties: - - name: Should be "dc-default-out". - nvidia,out-type: Output type. Should be TEGRA_DC_OUT_DSI or TEGRA_DC_OUT_HDMI. - - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. - - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. - nvidia,out-rotation: It specifies panel rotation in degree. - - nvidia,out-flags: One item or an array of several tuples items can be chosen. - List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, - TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, - TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, - TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, - TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. - If several items are written, bitwise OR is operated for them, internally. - - nvidia,out-parent-clk: Parent clk for display controller. - - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. - - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. - - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or - TEGRA_DC_ORDER_BLUE_RED. - - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for - BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, - BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, - and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. - For hdmi out-type case, depth selection is only valid for hdmi fb console mode, - otherwise, BASE_COLOR_SIZE888 is chosen as a default. - -1.C) NVIDIA Display Controller framebuffer data - This must be contained in dc parent node. This is required framebuffer data. - -Required properties: - - name: Should be "framebuffer-data". - nvidia,fb-bpp: Bits per pixel of fb. - nvidia,fb-flags: Window is updated in display controller device probe. Should be TEGRA_FB_FLIP_ON_PROBE, or 0 - - nvidia,fb-xres: Visible resolution for width. - - nvidia,fb-yres: Visible resolution for height. - -1.D) NVIDIA Display Controller Smart Dimmer Settings - This must be contained in dc parent node. This is smart dimmer settings. - - Required properties: - - name: Should be "smartdimmer". - - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control - signal directly. - - nvidia,hw-update-delay: It determines the delay of the update of the hardware - enhancement value (K) that is applied to the pixels. - - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. - 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment - of -1, indicates automatic based on aggressiveness. - - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. - - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. - - nvidia,phase-in-adjustments: Software backlight phase-in - - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) - rather than computed from nvidia,aggressiveness. - - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of - aggressiveness. - - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) - to a rectangular subset of display. - - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels - above nvidia,soft-clipping-threshold level to avoid saturation. - - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. - - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to - nvidia,smooth-k-incr. - - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed - at most by smooth-k-incr per frame. - - nvidia,coeff: Luminance calculation coefficients used to convert the red green and - blue color components into a luminance value. The conversion is performed according to - the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. - Need to write blue, green, red coefficient for luminance calculation in sequence. - - nvidia,fc: Flicker control that prevents rapid and frequent changes - in the enhancement value. Need to write time_limit, threshold in sequence. - - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to - write time_constant for the response curve and step that determines the instantaneous - portion of the target value of enhancement that is applied: <time_constant, step>. - - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve - defines how the backlight output changes with respect to the control input. The 17th point - is defined to be the maximum value. - - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k - for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). - There are nine entries in total. - - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. - - nvidia,bl-device-name: Backlight device name. - -1.E) NVIDIA Display Controller Color Management Unit Settings - This must be contained in dc parent node. This is color management unit settings. - - Required properties: - - name: Should be "cmu". - - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. - - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage, + HDMI_AVDD. + - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply. + - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source. Example + host1x { /* tegradc.0 */ dc@54200000 { + status = "okay"; compatible = "nvidia,tegra114-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; - status = "okay"; + nvidia,memory-clients = <2>; nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>; nvidia,emc-clk-rate = <204000000>; nvidia,cmu-enable = <1>; - avdd_hdmi-supply = <&palmas_ldoln>; - avdd_hdmi_pll-supply = <&palmas_ldo1>; - vdd_hdmi_5v0-supply = <&vdd_hdmi>; - dc-default-out { - nvidia,out-type = <TEGRA_DC_OUT_DSI>; - nvidia,out-width = <217>; - nvidia,out-height = <135>; - nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>; - nvidia,out-parent-clk = "pll_d_out0"; - }; - display-timings { - 1920p32 { - clock-frequency = <154700000>; - hactive = <1920>; - vactive = <1200>; - hfront-porch = <120>; - hback-porch = <32>; - hsync-len = <16>; - vfront-porch = <17>; - vback-porch = <16>; - vsync-len = <2>; - nvidia,h-ref-to-sync = <4>; - nvidia,v-ref-to-sync = <1>; - }; - }; - framebuffer-data { - nvidia,fb-bpp = <32>; /* bits per pixel */ - nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; - nvidia,fb-xres = <1920>; - nvidia,fb-yres = <1200>; - }; - smartdimmer { - status = "okay"; - nvidia,use-auto-pwm = <0>; - nvidia,hw-update-delay = <0>; - nvidia,bin-width = <0xffffffff>; - nvidia,aggressiveness = <5>; - nvidia,use-vid-luma = <0>; - nvidia,phase-in-settings = <0>; - nvidia,phase-in-adjustments = <0>; - nvidia,k-limit-enable = <1>; - nvidia,k-limit = <200>; - nvidia,sd-window-enable = <0>; - nvidia,soft-clipping-enable= <1>; - nvidia,soft-clipping-threshold = <128>; - nvidia,smooth-k-enable = <1>; - nvidia,smooth-k-incr = <4>; - nvidia,coeff = <5 9 2>; - nvidia,fc = <0 0>; - nvidia,blp = <1024 255>; - nvidia,bltf = <57 65 73 82 - 92 103 114 125 - 138 150 164 178 - 193 208 224 241>; - nvidia,lut = <255 255 255 - 199 199 199 - 153 153 153 - 116 116 116 - 85 85 85 - 59 59 59 - 36 36 36 - 17 17 17 - 0 0 0>; - nvidia,use-vpulse2 = <1>; - nvidia,bl-device-name = "pwm-backlight"; - }; - cmu { - status = "okay"; - nvidia,cmu-csc = < 0x138 0x3Ba 0x00D - 0x3F5 0x120 0x3E6 - 0x3FE 0x3F8 0x0E9 >; - nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6 - 7 8 9 10 11 11 12 13 - 13 14 15 15 16 17 17 18 - 18 19 19 20 20 21 21 22 - 22 23 23 23 24 24 24 25 - 25 25 26 26 26 27 27 27 - 28 28 28 28 29 29 29 29 - 30 30 30 30 31 31 31 31 - 32 32 32 32 33 33 33 33 - 34 34 34 35 35 35 35 36 - 36 36 37 37 37 37 38 38 - 38 39 39 39 39 40 40 40 - 41 41 41 41 42 42 42 43 - 43 43 43 44 44 44 45 45 - 45 45 46 46 46 46 47 47 - 47 47 48 48 48 48 49 49 - 49 49 50 50 50 50 50 51 - 51 51 51 52 52 52 52 52 - 53 53 53 53 53 53 54 54 - 54 54 54 55 55 55 55 55 - 55 56 56 56 56 56 56 57 - 57 57 57 57 57 57 58 58 - 58 58 58 58 59 59 59 59 - 59 59 59 60 60 60 60 60 - 60 60 61 61 61 61 61 61 - 61 62 62 62 62 62 62 62 - 63 63 63 63 63 63 63 64 - 64 64 64 64 64 64 65 65 - 65 65 65 65 66 66 66 66 - 66 66 66 67 67 67 67 67 - 67 68 68 68 68 68 68 69 - 69 69 69 69 69 70 70 70 - 70 70 70 71 71 71 71 71 - 71 72 72 72 72 72 72 73 - 73 73 73 73 73 74 74 74 - 74 74 74 74 75 75 75 75 - 75 75 76 76 76 76 76 76 - 77 77 77 77 77 77 77 78 - 78 78 78 78 78 79 79 79 - 79 79 79 79 80 80 80 80 - 80 80 80 80 81 81 81 81 - 81 81 81 82 82 82 82 82 - 82 82 82 83 83 83 83 83 - 83 83 83 83 84 84 84 84 - 84 84 84 84 85 85 85 85 - 85 85 85 85 85 85 86 86 - 86 86 86 86 86 86 86 86 - 87 87 87 87 87 87 87 87 - 87 87 88 88 88 88 88 88 - 88 88 88 88 88 88 89 89 - 89 89 89 89 89 89 89 89 - 89 89 90 90 90 90 90 90 - 90 90 90 90 90 90 91 91 - 91 91 91 91 91 91 91 91 - 91 91 91 92 92 92 92 92 - 92 92 92 92 92 92 92 92 - 93 93 93 93 93 93 93 93 - 93 93 93 93 93 93 94 94 - 94 94 94 94 94 94 94 94 - 94 94 94 94 95 95 95 95 - 95 95 95 95 95 95 95 95 - 95 96 96 96 96 96 96 96 - 96 96 96 96 96 96 97 97 - 97 97 97 97 97 97 97 97 - 98 99 99 100 101 101 102 103 - 103 104 105 105 106 107 107 108 - 109 110 110 111 112 112 113 114 - 114 115 115 116 117 117 118 119 - 119 120 120 121 121 122 123 123 - 124 124 125 125 126 126 127 128 - 128 129 129 130 130 131 131 132 - 132 133 133 134 134 135 135 136 - 136 137 138 138 139 139 140 140 - 141 141 142 142 143 143 144 144 - 144 145 145 146 146 147 147 148 - 148 149 149 150 150 151 151 152 - 152 153 153 153 154 154 155 155 - 156 156 157 157 157 158 158 159 - 159 160 160 160 161 161 162 162 - 162 163 163 164 164 164 165 165 - 165 166 166 167 167 167 168 168 - 168 169 169 169 170 170 171 171 - 171 172 172 172 173 173 173 174 - 174 174 175 175 175 176 176 176 - 177 177 177 178 178 178 179 179 - 179 180 180 180 181 181 181 182 - 182 182 183 183 183 184 184 184 - 185 185 185 185 186 186 186 187 - 187 187 188 188 188 189 189 189 - 190 190 190 191 191 191 191 192 - 192 192 193 193 193 194 194 194 - 195 195 195 195 196 196 196 197 - 197 197 198 198 198 199 199 199 - 199 200 200 200 201 201 201 202 - 202 202 203 203 203 203 204 204 - 204 205 205 205 206 206 206 207 - 207 207 208 208 208 208 209 209 - 209 210 210 210 211 211 211 212 - 212 212 213 213 213 214 214 214 - 215 215 215 215 216 216 216 217 - 217 217 218 218 218 219 219 219 - 220 220 220 220 221 221 221 222 - 222 222 222 223 223 223 224 224 - 224 224 225 225 225 226 226 226 - 226 227 227 227 227 228 228 228 - 229 229 229 229 230 230 230 230 - 230 231 231 231 231 232 232 232 - 232 233 233 233 233 234 234 234 - 234 234 235 235 235 235 236 236 - 236 236 236 237 237 237 237 238 - 238 238 238 238 239 239 239 239 - 239 240 240 240 240 240 241 241 - 241 241 241 242 242 242 242 243 - 243 243 243 243 244 244 244 244 - 244 245 245 245 245 245 246 246 - 246 246 246 247 247 247 247 248 - 248 248 248 248 249 249 249 249 - 250 250 250 250 251 251 251 251 - 251 252 252 252 253 253 253 253 - 254 254 254 254 255 255 255 255 >; - }; + nvidia,low-v-win = <0x2>; + nvidia,out-type = <TEGRA_DC_OUT_DSI>; + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; }; - /* tegradc.1 */ dc@54240000 { + status = "okay"; compatible = "nvidia,tegra114-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; - status = "okay"; + nvidia,memory-clients = <3>; nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>; nvidia,emc-clk-rate = <300000000>; - nvidia,cmu-enable = <1>; - dc-default-out { - nvidia,out-type = <TEGRA_DC_OUT_HDMI>; - nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH TEGRA_DC_OUT_HOTPLUG_WAKE_LP0>; - nvidia,out-parent-clk = "pll_d2"; - nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ - nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; - nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; - }; - framebuffer-data { - nvidia,fb-bpp = <32>; /* bits per pixel */ - nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; - nvidia,fb-xres = <1280>; - nvidia,fb-yres = <720>; - }; + nvidia,out-type = <TEGRA_DC_OUT_HDMI>; + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; + avdd_hdmi-supply = <&palmas_ldoln>; + avdd_hdmi_pll-supply = <&palmas_ldo1>; + vdd_hdmi_5v0-supply = <&vdd_hdmi>; }; - }; + } diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt index c826f37bad8f..03c7c4986158 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-dsi.txt @@ -16,6 +16,7 @@ NVIDIA TEGRA114 Display Serial Interface 1.A) dsi panel node: dsi panel node must be contained in dsi parent node. This node represents dsi panel node. + It is possible to have multiple dsi panel nodes. Required properties - name: Can be arbitrary. @@ -34,11 +35,17 @@ NVIDIA TEGRA114 Display Serial Interface TEGRA_DSI_PIXEL_FORMAT_18BIT_P, TEGRA_DSI_PIXEL_FORMAT_18BIT_NP and TEGRA_DSI_PIXEL_FORMAT_24BIT_P, respectively. - nvidia,dsi-refresh-rate: Refresh rate. + - nvidia,dsi-rated-refresh-rate: dsi rated Refresh rate. - nvidia,dsi-virtual-channel: DSI virtual channel number. Write 0, 1, 2 and 3 for TEGRA_DSI_VIRTUAL_CHANNEL_0, TEGRA_DSI_VIRTUAL_CHANNEL_1, TEGRA_DSI_VIRTUAL_CHANNEL_2 and TEGRA_DSI_VIRTUAL_CHANNEL_3, respectively. - nvidia,dsi-instance: Should be 0 or 1: DSI controller or DSIB controller. - nvidia,dsi-panel-reset: Indicate if dsi output device requires hardware reset or not. + - nvidia,dsi-te-polarity-low: 1 if dsi panel te polarity is low. - nvidia,dsi-power-saving-suspend: With enabled, set dsi controller ultra low power mode in suspend. + - nvidia,dsi-lp00-pre-panel-wakeup: With 1, maintain dsi lp-00 before panel wake-up + - nvidia,dsi-bl-name: Backlight device name. It may be same with nvidia,bl-device-name. + - nvidia,dsi-suspend-aggr: DSI suspend aggressiveness. DSI_HOST_SUSPEND_LV2, DSI_HOST_SUSPEND_LV1, + DSI_HOST_SUSPEND_LV0 or DSI_NO_SUSPEND can be set. - nvidia,dsi-ulpm-not-support: With enabled, do not enter dsi ulpm mode. - nvidia,dsi-video-data-type: The DSI operates in two transmission modes: video and host/command. Write 0, 1 for TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, respectively. @@ -72,48 +79,330 @@ NVIDIA TEGRA114 Display Serial Interface - nvidia,dsi-phy-tasure: dsi phy timing, t_tasure_ns. - nvidia,dsi-phy-tago: dsi phy timing, t_tago_ns. + - Child nodes represent node of modes, output settings, + smart dimmer settings, color management unit settings. + +1.A.i) NVIDIA Display Controller Modes + This must be contained in dsi panel parent node. This contains supported modes. + + Required properties: + - name: Should be "display-timings" + + - Child nodes represent modes. Several modes can be prepared. + +1.A.i.x) NVIDIA Display Controller Mode timing + This must be contained in display-timings parent node. This contains mode settings, including + display timings. For hdmi out-type case, display-timings properties are only valid in case of + hdmi fb console mode. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - hactive, vactive: display resolution. + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels. + - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines. + - clock-frequency: display clock in Hz. + - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC + with respect to H reference point. + - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC + with respect to V reference point. + +1.A.j) NVIDIA Display Default Output Settings + This must be contained in dsi panel parent node. This is default output settings. + + Required properties: + - name: Should be "disp-default-out". + - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. + - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. + - nvidia,out-flags: One item or an array of several tuples items can be chosen. + List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, + TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, + TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, + TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. + If several items are written, bitwise OR is operated for them, internally. + - nvidia,out-parent-clk: Parent clk for display controller. + - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. + - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. + - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or + TEGRA_DC_ORDER_BLUE_RED. + - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for + BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, + BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, + and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. + For hdmi out-type case, depth selection is only valid for hdmi fb console mode, + otherwise, BASE_COLOR_SIZE888 is chosen as a default. + - nvidia,out-xres: Visible resolution for width. + - nvidia,out-yres: Visible resolution for height. + +1.A.k) NVIDIA Display Controller Smart Dimmer Settings + This must be contained in dsi panel parent node. This is smart dimmer settings. + + Required properties: + - name: Should be "smartdimmer". + - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control + signal directly. + - nvidia,hw-update-delay: It determines the delay of the update of the hardware + enhancement value (K) that is applied to the pixels. + - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. + 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment + of -1, indicates automatic based on aggressiveness. + - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. + - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. + - nvidia,phase-in-adjustments: Software backlight phase-in + - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) + rather than computed from nvidia,aggressiveness. + - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of + aggressiveness. + - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) + to a rectangular subset of display. + - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels + above nvidia,soft-clipping-threshold level to avoid saturation. + - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. + - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to + nvidia,smooth-k-incr. + - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed + at most by smooth-k-incr per frame. + - nvidia,coeff: Luminance calculation coefficients used to convert the red green and + blue color components into a luminance value. The conversion is performed according to + the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. + Need to write blue, green, red coefficient for luminance calculation in sequence. + - nvidia,fc: Flicker control that prevents rapid and frequent changes + in the enhancement value. Need to write time_limit, threshold in sequence. + - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to + write time_constant for the response curve and step that determines the instantaneous + portion of the target value of enhancement that is applied: <time_constant, step>. + - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve + defines how the backlight output changes with respect to the control input. The 17th point + is defined to be the maximum value. + - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k + for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). + There are nine entries in total. + - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. + - nvidia,bl-device-name: Backlight device name. + +1.A.l) NVIDIA Display Controller Color Management Unit Settings + This must be contained in dsi parent node. This is color management unit settings. + + Required properties: + - name: Should be "cmu". + - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. + - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + Example + host1x { dsi { + status = "okay"; compatible = "nvidia,tegra114-dsi"; reg = <0x54300000 0x00040000>, <0x54400000 0x00040000>; - status = "okay"; - nvidia,dsi-controller-vs = <1>; - panel-l-wxga-7 { + nvidia,dsi-controller-vs = <DSI_VS_1>; + panel-p-wuxga-10-1 { status = "okay"; - compatible = "lg,wxga-7"; - nvidia,dsi-instance = <0>; + compatible = "p,wuxga-10-1"; + nvidia,dsi-instance = <DSI_INSTANCE_0>; nvidia,dsi-n-data-lanes = <4>; - nvidia,dsi-pixel-format = <3>; + nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>; nvidia,dsi-refresh-rate = <60>; - nvidia,dsi-video-data-type = <0>; - nvidia,dsi-video-clock-mode = <0>; - nvidia,dsi-video-burst-mode = <0>; - nvidia,dsi-virtual-channel = <0>; - nvidia,dsi-power-saving-suspend = <1>; - nvidia,dsi-phy-datzero = <270>; - nvidia,dsi-phy-hsprepare = <30>; - nvidia,dsi-phy-clkzero = <330>; - nvidia,dsi-phy-clkprepare = <27>; - nvidia,dsi-init-cmd = <0x0 0x15 0x01 0x0 0x0>, - <1 20>, - <0x0 0x15 0xae 0x0b 0x0>, - <0x0 0x15 0xee 0xea 0x0>, - <0x0 0x15 0xef 0x5f 0x0>, - <0x0 0x15 0xf2 0x68 0x0>, - <0x0 0x15 0xee 0x0 0x0>, - <0x0 0x15 0xef 0x0 0x0>; - nvidia,dsi-n-init-cmd = <8>; - nvidia,dsi-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, - <1 160>; - nvidia,dsi-n-suspend-cmd = <2>; - nvidia,dsi-late-resume-cmd = <0x0 0x15 0x10 0x0 0x0>, - <1 120>; - nvidia,dsi-n-late-resume-cmd = <2>; - nvidia,dsi-early-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, - <1 160>; - nvidia,dsi-n-early-suspend-cmd = <2>; + nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>; + nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>; + nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>; + nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>; + nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>; + nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>; + nvidia,dsi-panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(H, 1) 0>; /* PH1 */ + nvidia,dsi-pkt-seq = + <CMD_VS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_VE LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>; + disp-default-out { + nvidia,out-width = <217>; + nvidia,out-height = <135>; + nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>; + nvidia,out-parent-clk = "pll_d_out0"; + nvidia,out-xres = <1920>; + nvidia,out-yres = <1200>; + }; + display-timings { + 1920x1200-32 { + clock-frequency = <154700000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <120>; + hback-porch = <32>; + hsync-len = <16>; + vfront-porch = <17>; + vback-porch = <16>; + vsync-len = <2>; + nvidia,h-ref-to-sync = <4>; + nvidia,v-ref-to-sync = <1>; + }; + }; + smartdimmer { + status = "okay"; + nvidia,use-auto-pwm = <0>; + nvidia,hw-update-delay = <0>; + nvidia,bin-width = <0xffffffff>; + nvidia,aggressiveness = <5>; + nvidia,use-vid-luma = <0>; + nvidia,phase-in-settings = <0>; + nvidia,phase-in-adjustments = <0>; + nvidia,k-limit-enable = <1>; + nvidia,k-limit = <200>; + nvidia,sd-window-enable = <0>; + nvidia,soft-clipping-enable= <1>; + nvidia,soft-clipping-threshold = <128>; + nvidia,smooth-k-enable = <1>; + nvidia,smooth-k-incr = <4>; + nvidia,coeff = <5 9 2>; + nvidia,fc = <0 0>; + nvidia,blp = <1024 255>; + nvidia,bltf = <57 65 73 82 + 92 103 114 125 + 138 150 164 178 + 193 208 224 241>; + nvidia,lut = <255 255 255 + 199 199 199 + 153 153 153 + 116 116 116 + 85 85 85 + 59 59 59 + 36 36 36 + 17 17 17 + 0 0 0>; + nvidia,use-vpulse2 = <1>; + nvidia,bl-device-name = "pwm-backlight"; + }; + cmu { + nvidia,cmu-csc = < 0x138 0x3ba 0x00d + 0x3f5 0x120 0x3e6 + 0x3fe 0x3f8 0x0e9 >; + nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6 + 7 8 9 10 11 11 12 13 + 13 14 15 15 16 17 17 18 + 18 19 19 20 20 21 21 22 + 22 23 23 23 24 24 24 25 + 25 25 26 26 26 27 27 27 + 28 28 28 28 29 29 29 29 + 30 30 30 30 31 31 31 31 + 32 32 32 32 33 33 33 33 + 34 34 34 35 35 35 35 36 + 36 36 37 37 37 37 38 38 + 38 39 39 39 39 40 40 40 + 41 41 41 41 42 42 42 43 + 43 43 43 44 44 44 45 45 + 45 45 46 46 46 46 47 47 + 47 47 48 48 48 48 49 49 + 49 49 50 50 50 50 50 51 + 51 51 51 52 52 52 52 52 + 53 53 53 53 53 53 54 54 + 54 54 54 55 55 55 55 55 + 55 56 56 56 56 56 56 57 + 57 57 57 57 57 57 58 58 + 58 58 58 58 59 59 59 59 + 59 59 59 60 60 60 60 60 + 60 60 61 61 61 61 61 61 + 61 62 62 62 62 62 62 62 + 63 63 63 63 63 63 63 64 + 64 64 64 64 64 64 65 65 + 65 65 65 65 66 66 66 66 + 66 66 66 67 67 67 67 67 + 67 68 68 68 68 68 68 69 + 69 69 69 69 69 70 70 70 + 70 70 70 71 71 71 71 71 + 71 72 72 72 72 72 72 73 + 73 73 73 73 73 74 74 74 + 74 74 74 74 75 75 75 75 + 75 75 76 76 76 76 76 76 + 77 77 77 77 77 77 77 78 + 78 78 78 78 78 79 79 79 + 79 79 79 79 80 80 80 80 + 80 80 80 80 81 81 81 81 + 81 81 81 82 82 82 82 82 + 82 82 82 83 83 83 83 83 + 83 83 83 83 84 84 84 84 + 84 84 84 84 85 85 85 85 + 85 85 85 85 85 85 86 86 + 86 86 86 86 86 86 86 86 + 87 87 87 87 87 87 87 87 + 87 87 88 88 88 88 88 88 + 88 88 88 88 88 88 89 89 + 89 89 89 89 89 89 89 89 + 89 89 90 90 90 90 90 90 + 90 90 90 90 90 90 91 91 + 91 91 91 91 91 91 91 91 + 91 91 91 92 92 92 92 92 + 92 92 92 92 92 92 92 92 + 93 93 93 93 93 93 93 93 + 93 93 93 93 93 93 94 94 + 94 94 94 94 94 94 94 94 + 94 94 94 94 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 96 96 96 96 96 96 96 + 96 96 96 96 96 96 97 97 + 97 97 97 97 97 97 97 97 + 98 99 99 100 101 101 102 103 + 103 104 105 105 106 107 107 108 + 109 110 110 111 112 112 113 114 + 114 115 115 116 117 117 118 119 + 119 120 120 121 121 122 123 123 + 124 124 125 125 126 126 127 128 + 128 129 129 130 130 131 131 132 + 132 133 133 134 134 135 135 136 + 136 137 138 138 139 139 140 140 + 141 141 142 142 143 143 144 144 + 144 145 145 146 146 147 147 148 + 148 149 149 150 150 151 151 152 + 152 153 153 153 154 154 155 155 + 156 156 157 157 157 158 158 159 + 159 160 160 160 161 161 162 162 + 162 163 163 164 164 164 165 165 + 165 166 166 167 167 167 168 168 + 168 169 169 169 170 170 171 171 + 171 172 172 172 173 173 173 174 + 174 174 175 175 175 176 176 176 + 177 177 177 178 178 178 179 179 + 179 180 180 180 181 181 181 182 + 182 182 183 183 183 184 184 184 + 185 185 185 185 186 186 186 187 + 187 187 188 188 188 189 189 189 + 190 190 190 191 191 191 191 192 + 192 192 193 193 193 194 194 194 + 195 195 195 195 196 196 196 197 + 197 197 198 198 198 199 199 199 + 199 200 200 200 201 201 201 202 + 202 202 203 203 203 203 204 204 + 204 205 205 205 206 206 206 207 + 207 207 208 208 208 208 209 209 + 209 210 210 210 211 211 211 212 + 212 212 213 213 213 214 214 214 + 215 215 215 215 216 216 216 217 + 217 217 218 218 218 219 219 219 + 220 220 220 220 221 221 221 222 + 222 222 222 223 223 223 224 224 + 224 224 225 225 225 226 226 226 + 226 227 227 227 227 228 228 228 + 229 229 229 229 230 230 230 230 + 230 231 231 231 231 232 232 232 + 232 233 233 233 233 234 234 234 + 234 234 235 235 235 235 236 236 + 236 236 236 237 237 237 237 238 + 238 238 238 238 239 239 239 239 + 239 240 240 240 240 240 241 241 + 241 241 241 242 242 242 242 243 + 243 243 243 243 244 244 244 244 + 244 245 245 245 245 245 246 246 + 246 246 246 247 247 247 247 248 + 248 248 248 248 249 249 249 249 + 250 250 250 250 251 251 251 251 + 251 252 252 252 253 253 253 253 + 254 254 254 254 255 255 255 255 >; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt index 5fd7b27fdedb..76197a49bc46 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra114-hdmi.txt @@ -19,16 +19,133 @@ NVIDIA TEGRA114 High Definition Multimedia Interface which does only set DDC_SDA and DDC_SCL pull downs to be active when hotplug is detected, otherwise keep them disabled. - 1.B) NVIDIA HDMI TMDS configurations - This must be contained in hdmi parent node. This includes tmds configurations. + 1.A) The hdmi-display node: + hdmi-display must be contained in hdmi parent node. This node represents hdmi display node. + + Required properties + - name: hdmi-display + + - Child nodes represent tmds configurations, node of modes, output settings, + smart dimmer settings, color management unit settings. + + 1.A.i) NVIDIA Display Controller Modes + This must be contained in hdmi-display parent node. This contains supported modes. Required properties: - - name: Should be "nvidia,out-tmds-cfg" + - name: Should be "display-timings" + + - Child nodes represent modes. Several modes can be prepared. + + 1.A.i.x) NVIDIA Display Controller Mode timing + This must be contained in display-timings parent node. This contains mode settings, including + display timings. For hdmi out-type case, display-timings properties are only valid in case of + hdmi fb console mode. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - hactive, vactive: display resolution. + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels. + - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines. + - clock-frequency: display clock in Hz. + - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC + with respect to H reference point. + - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC + with respect to V reference point. + + 1.A.j) NVIDIA Display Default Output Settings + This must be contained in hdmi-display parent node. This is default output settings. + + Required properties: + - name: Should be "disp-default-out". + - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. + - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. + - nvidia,out-flags: One item or an array of several tuples items can be chosen. + List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, + TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, + TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, + TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. + If several items are written, bitwise OR is operated for them, internally. + - nvidia,out-parent-clk: Parent clk for display controller. + - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. + - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. + - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or + TEGRA_DC_ORDER_BLUE_RED. + - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for + BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, + BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, + and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. + For hdmi out-type case, depth selection is only valid for hdmi fb console mode, + otherwise, BASE_COLOR_SIZE888 is chosen as a default. + - nvidia,out-xres: Visible resolution for width. + - nvidia,out-yres: Visible resolution for height. + + 1.A.k) NVIDIA Display Controller Smart Dimmer Settings + This must be contained in hdmi-display parent node. This is smart dimmer settings. + + Required properties: + - name: Should be "smartdimmer". + - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control + signal directly. + - nvidia,hw-update-delay: It determines the delay of the update of the hardware + enhancement value (K) that is applied to the pixels. + - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. + 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment + of -1, indicates automatic based on aggressiveness. + - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. + - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. + - nvidia,phase-in-adjustments: Software backlight phase-in + - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) + rather than computed from nvidia,aggressiveness. + - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of + aggressiveness. + - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) + to a rectangular subset of display. + - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels + above nvidia,soft-clipping-threshold level to avoid saturation. + - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. + - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to + nvidia,smooth-k-incr. + - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed + at most by smooth-k-incr per frame. + - nvidia,coeff: Luminance calculation coefficients used to convert the red green and + blue color components into a luminance value. The conversion is performed according to + the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. + Need to write blue, green, red coefficient for luminance calculation in sequence. + - nvidia,fc: Flicker control that prevents rapid and frequent changes + in the enhancement value. Need to write time_limit, threshold in sequence. + - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to + write time_constant for the response curve and step that determines the instantaneous + portion of the target value of enhancement that is applied: <time_constant, step>. + - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve + defines how the backlight output changes with respect to the control input. The 17th point + is defined to be the maximum value. + - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k + for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). + There are nine entries in total. + - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. + - nvidia,bl-device-name: Backlight device name. + + 1.A.l) NVIDIA Display Controller Color Management Unit Settings + This must be contained in hdmi-display node. This is color management unit settings. + + Required properties: + - name: Should be "cmu". + - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. + - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + + 1.A.m) NVIDIA HDMI TMDS configurations + This must be contained in hdmi-display parent node. This includes tmds configurations. + + Required properties: + - name: Should be "tmds-config" - Child nodes represent tmds configurations. Several configurations can be prepared. - 1.B.i) NVIDIA HDMI TMDS configuration - This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration. + 1.A.m.x) NVIDIA HDMI TMDS configuration + This must be contained in tmds-config parent node. This includes tmds configuration. Required properties: - name: Can be arbitrary, but each sibling node should have unique name. @@ -46,13 +163,75 @@ NVIDIA TEGRA114 High Definition Multimedia Interface - pad-ctls0-setting: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register or mask. Example + host1x { hdmi { + status = "okay"; compatible = "nvidia,tegra114-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <0 75 0x04>; - status = "okay"; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 1>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 1>; /* PN7 */ + hdmi-display { + status = "okay"; + disp-default-out { + nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH>; + nvidia,out-parent-clk = "pll_d2"; + nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ + nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; + nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; + nvidia,out-xres = <1920>; + nvidia,out-yres = <1080>; + }; + tmds-config { + tmds-cfg@0 { + version = <1 0>; + pclk = <27000000>; + pll0 = <0x01003010>; + pll1 = <0x00301b00>; + pe-current = <0x00000000>; + drive-current = <0x1f1f1f1f>; + peak-current = <0x03030303>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000400>; + }; + tmds-cfg@1 { + version = <1 0>; + pclk = <74250000>; + pll0 = <0x01003110>; + pll1 = <0x00301500>; + pe-current = <0x00000000>; + drive-current = <0x2c2c2c2c>; + peak-current = <0x07070707>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000400>; + }; + tmds-cfg@2 { + version = <1 0>; + pclk = <148500000>; + pll0 = <0x01003310>; + pll1 = <0x00301500>; + pe-current = <0x00000000>; + drive-current = <0x33333333>; + peak-current = <0x0c0c0c0c>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000400>; + }; + tmds-cfg@3 { + version = <1 0>; + pclk = <0x7fffffff>; + pll0 = <0x01003f10>; + pll1 = <0x00300f00>; + pe-current = <0x00000000>; + drive-current = <0x37373737>; + peak-current = <0x17171717>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000600>; + }; + }; + }; }; }; + hdmi_ddc: i2c@7000c700 { + clock-frequency = <100000>; + }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt index ca1f5e733bac..940e9e058063 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-dc.txt @@ -17,361 +17,48 @@ NVIDIA Tegra124 Display Controller - nvidia,cmu-enable: Toggle switch for color management unit. - nvidia,low-v-win: If low_v_win is set, we can lower vdd_core when that windows is the only one active. - - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage, - HDMI_AVDD. - - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply. - - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source. - - - Child nodes represent node of modes, output settings, framebuffer data, - smart dimmer settings, color management unit settings, dsi output device settings. - -1.A) NVIDIA Display Controller Modes - This must be contained in dc parent node. This contains supported modes. - - Required properties: - - name: Should be "display-timings" - - - Child nodes represent modes. Several modes can be prepared. - -1.A.i) NVIDIA Display Controller Mode timing - This must be contained in display-timings parent node. This contains mode settings, including - display timings. For hdmi out-type case, display-timings properties are only valid in case of - hdmi fb console mode. - - Required properties: - - name: Can be arbitrary, but each sibling node should have unique name. - - hactive, vactive: display resolution. - - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters - in pixels. - - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in - lines. - - clock-frequency: display clock in Hz. - - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC - with respect to H reference point. - - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC - with respect to V reference point. - -1.B) NVIDIA Display Controller Default Output Settings - This must be contained in dc parent node. This is default output settings. - - Required properties: - - name: Should be "dc-default-out". - nvidia,out-type: Output type. Should be TEGRA_DC_OUT_DSI or TEGRA_DC_OUT_HDMI. - - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. - - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. - nvidia,out-rotation: It specifies panel rotation in degree. - - nvidia,out-flags: One item or an array of several tuples items can be chosen. - List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, - TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, - TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, - TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, - TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. - If several items are written, bitwise OR is operated for them, internally. - - nvidia,out-parent-clk: Parent clk for display controller. - - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. - - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. - - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or - TEGRA_DC_ORDER_BLUE_RED. - - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for - BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, - BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, - and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. - For hdmi out-type case, depth selection is only valid for hdmi fb console mode, - otherwise, BASE_COLOR_SIZE888 is chosen as a default. - -1.C) NVIDIA Display Controller framebuffer data - This must be contained in dc parent node. This is required framebuffer data. - -Required properties: - - name: Should be "framebuffer-data". - nvidia,fb-bpp: Bits per pixel of fb. - nvidia,fb-flags: Window is updated in display controller device probe. Should be TEGRA_FB_FLIP_ON_PROBE, or 0 - - nvidia,fb-xres: Visible resolution for width. - - nvidia,fb-yres: Visible resolution for height. - -1.D) NVIDIA Display Controller Smart Dimmer Settings - This must be contained in dc parent node. This is smart dimmer settings. - - Required properties: - - name: Should be "smartdimmer". - - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control - signal directly. - - nvidia,hw-update-delay: It determines the delay of the update of the hardware - enhancement value (K) that is applied to the pixels. - - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. - 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment - of -1, indicates automatic based on aggressiveness. - - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. - - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. - - nvidia,phase-in-adjustments: Software backlight phase-in - - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) - rather than computed from nvidia,aggressiveness. - - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of - aggressiveness. - - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) - to a rectangular subset of display. - - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels - above nvidia,soft-clipping-threshold level to avoid saturation. - - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. - - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to - nvidia,smooth-k-incr. - - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed - at most by smooth-k-incr per frame. - - nvidia,coeff: Luminance calculation coefficients used to convert the red green and - blue color components into a luminance value. The conversion is performed according to - the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. - Need to write blue, green, red coefficient for luminance calculation in sequence. - - nvidia,fc: Flicker control that prevents rapid and frequent changes - in the enhancement value. Need to write time_limit, threshold in sequence. - - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to - write time_constant for the response curve and step that determines the instantaneous - portion of the target value of enhancement that is applied: <time_constant, step>. - - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve - defines how the backlight output changes with respect to the control input. The 17th point - is defined to be the maximum value. - - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k - for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). - There are nine entries in total. - - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. - - nvidia,bl-device-name: Backlight device name. - -1.E) NVIDIA Display Controller Color Management Unit Settings - This must be contained in dc parent node. This is color management unit settings. - - Required properties: - - name: Should be "cmu". - - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. - - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + - avdd_hdmi-supply: phandle to the regulator device tree node for HDMI supply voltage, + HDMI_AVDD. + - avdd_hdmi_pll-supply: phandle to the regulator device tree node for HDMI pll supply. + - vdd_hdmi_5v0-supply: phandle to the regulator device tree node for HDMI 5V source. Example + host1x { /* tegradc.0 */ dc@54200000 { + status = "okay"; compatible = "nvidia,tegra124-dc"; reg = <0x54200000 0x00040000>; interrupts = <0 73 0x04>; - status = "okay"; + nvidia,memory-clients = <2>; nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>; nvidia,emc-clk-rate = <204000000>; nvidia,cmu-enable = <1>; - avdd_hdmi-supply = <&palmas_ldoln>; - avdd_hdmi_pll-supply = <&palmas_ldo1>; - vdd_hdmi_5v0-supply = <&vdd_hdmi>; - dc-default-out { - nvidia,out-type = <TEGRA_DC_OUT_DSI>; - nvidia,out-width = <217>; - nvidia,out-height = <135>; - nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>; - nvidia,out-parent-clk = "pll_d_out0"; - }; - display-timings { - 1920p32 { - clock-frequency = <154700000>; - hactive = <1920>; - vactive = <1200>; - hfront-porch = <120>; - hback-porch = <32>; - hsync-len = <16>; - vfront-porch = <17>; - vback-porch = <16>; - vsync-len = <2>; - nvidia,h-ref-to-sync = <4>; - nvidia,v-ref-to-sync = <1>; - }; - }; - framebuffer-data { - nvidia,fb-bpp = <32>; /* bits per pixel */ - nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; - nvidia,fb-xres = <1920>; - nvidia,fb-yres = <1200>; - }; - smartdimmer { - status = "okay"; - nvidia,use-auto-pwm = <0>; - nvidia,hw-update-delay = <0>; - nvidia,bin-width = <0xffffffff>; - nvidia,aggressiveness = <5>; - nvidia,use-vid-luma = <0>; - nvidia,phase-in-settings = <0>; - nvidia,phase-in-adjustments = <0>; - nvidia,k-limit-enable = <1>; - nvidia,k-limit = <200>; - nvidia,sd-window-enable = <0>; - nvidia,soft-clipping-enable= <1>; - nvidia,soft-clipping-threshold = <128>; - nvidia,smooth-k-enable = <1>; - nvidia,smooth-k-incr = <4>; - nvidia,coeff = <5 9 2>; - nvidia,fc = <0 0>; - nvidia,blp = <1024 255>; - nvidia,bltf = <57 65 73 82 - 92 103 114 125 - 138 150 164 178 - 193 208 224 241>; - nvidia,lut = <255 255 255 - 199 199 199 - 153 153 153 - 116 116 116 - 85 85 85 - 59 59 59 - 36 36 36 - 17 17 17 - 0 0 0>; - nvidia,use-vpulse2 = <1>; - nvidia,bl-device-name = "pwm-backlight"; - }; - cmu { - status = "okay"; - nvidia,cmu-csc = < 0x138 0x3Ba 0x00D - 0x3F5 0x120 0x3E6 - 0x3FE 0x3F8 0x0E9 >; - nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6 - 7 8 9 10 11 11 12 13 - 13 14 15 15 16 17 17 18 - 18 19 19 20 20 21 21 22 - 22 23 23 23 24 24 24 25 - 25 25 26 26 26 27 27 27 - 28 28 28 28 29 29 29 29 - 30 30 30 30 31 31 31 31 - 32 32 32 32 33 33 33 33 - 34 34 34 35 35 35 35 36 - 36 36 37 37 37 37 38 38 - 38 39 39 39 39 40 40 40 - 41 41 41 41 42 42 42 43 - 43 43 43 44 44 44 45 45 - 45 45 46 46 46 46 47 47 - 47 47 48 48 48 48 49 49 - 49 49 50 50 50 50 50 51 - 51 51 51 52 52 52 52 52 - 53 53 53 53 53 53 54 54 - 54 54 54 55 55 55 55 55 - 55 56 56 56 56 56 56 57 - 57 57 57 57 57 57 58 58 - 58 58 58 58 59 59 59 59 - 59 59 59 60 60 60 60 60 - 60 60 61 61 61 61 61 61 - 61 62 62 62 62 62 62 62 - 63 63 63 63 63 63 63 64 - 64 64 64 64 64 64 65 65 - 65 65 65 65 66 66 66 66 - 66 66 66 67 67 67 67 67 - 67 68 68 68 68 68 68 69 - 69 69 69 69 69 70 70 70 - 70 70 70 71 71 71 71 71 - 71 72 72 72 72 72 72 73 - 73 73 73 73 73 74 74 74 - 74 74 74 74 75 75 75 75 - 75 75 76 76 76 76 76 76 - 77 77 77 77 77 77 77 78 - 78 78 78 78 78 79 79 79 - 79 79 79 79 80 80 80 80 - 80 80 80 80 81 81 81 81 - 81 81 81 82 82 82 82 82 - 82 82 82 83 83 83 83 83 - 83 83 83 83 84 84 84 84 - 84 84 84 84 85 85 85 85 - 85 85 85 85 85 85 86 86 - 86 86 86 86 86 86 86 86 - 87 87 87 87 87 87 87 87 - 87 87 88 88 88 88 88 88 - 88 88 88 88 88 88 89 89 - 89 89 89 89 89 89 89 89 - 89 89 90 90 90 90 90 90 - 90 90 90 90 90 90 91 91 - 91 91 91 91 91 91 91 91 - 91 91 91 92 92 92 92 92 - 92 92 92 92 92 92 92 92 - 93 93 93 93 93 93 93 93 - 93 93 93 93 93 93 94 94 - 94 94 94 94 94 94 94 94 - 94 94 94 94 95 95 95 95 - 95 95 95 95 95 95 95 95 - 95 96 96 96 96 96 96 96 - 96 96 96 96 96 96 97 97 - 97 97 97 97 97 97 97 97 - 98 99 99 100 101 101 102 103 - 103 104 105 105 106 107 107 108 - 109 110 110 111 112 112 113 114 - 114 115 115 116 117 117 118 119 - 119 120 120 121 121 122 123 123 - 124 124 125 125 126 126 127 128 - 128 129 129 130 130 131 131 132 - 132 133 133 134 134 135 135 136 - 136 137 138 138 139 139 140 140 - 141 141 142 142 143 143 144 144 - 144 145 145 146 146 147 147 148 - 148 149 149 150 150 151 151 152 - 152 153 153 153 154 154 155 155 - 156 156 157 157 157 158 158 159 - 159 160 160 160 161 161 162 162 - 162 163 163 164 164 164 165 165 - 165 166 166 167 167 167 168 168 - 168 169 169 169 170 170 171 171 - 171 172 172 172 173 173 173 174 - 174 174 175 175 175 176 176 176 - 177 177 177 178 178 178 179 179 - 179 180 180 180 181 181 181 182 - 182 182 183 183 183 184 184 184 - 185 185 185 185 186 186 186 187 - 187 187 188 188 188 189 189 189 - 190 190 190 191 191 191 191 192 - 192 192 193 193 193 194 194 194 - 195 195 195 195 196 196 196 197 - 197 197 198 198 198 199 199 199 - 199 200 200 200 201 201 201 202 - 202 202 203 203 203 203 204 204 - 204 205 205 205 206 206 206 207 - 207 207 208 208 208 208 209 209 - 209 210 210 210 211 211 211 212 - 212 212 213 213 213 214 214 214 - 215 215 215 215 216 216 216 217 - 217 217 218 218 218 219 219 219 - 220 220 220 220 221 221 221 222 - 222 222 222 223 223 223 224 224 - 224 224 225 225 225 226 226 226 - 226 227 227 227 227 228 228 228 - 229 229 229 229 230 230 230 230 - 230 231 231 231 231 232 232 232 - 232 233 233 233 233 234 234 234 - 234 234 235 235 235 235 236 236 - 236 236 236 237 237 237 237 238 - 238 238 238 238 239 239 239 239 - 239 240 240 240 240 240 241 241 - 241 241 241 242 242 242 242 243 - 243 243 243 243 244 244 244 244 - 244 245 245 245 245 245 246 246 - 246 246 246 247 247 247 247 248 - 248 248 248 248 249 249 249 249 - 250 250 250 250 251 251 251 251 - 251 252 252 252 253 253 253 253 - 254 254 254 254 255 255 255 255 >; - }; + nvidia,low-v-win = <0x2>; + nvidia,out-type = <TEGRA_DC_OUT_DSI>; + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; }; - /* tegradc.1 */ dc@54240000 { + status = "okay"; compatible = "nvidia,tegra124-dc"; reg = <0x54240000 0x00040000>; interrupts = <0 74 0x04>; - status = "okay"; + nvidia,memory-clients = <3>; nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>; nvidia,emc-clk-rate = <300000000>; - nvidia,cmu-enable = <1>; - dc-default-out { - nvidia,out-type = <TEGRA_DC_OUT_HDMI>; - nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH TEGRA_DC_OUT_HOTPLUG_WAKE_LP0>; - nvidia,out-parent-clk = "pll_d2"; - nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ - nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; - nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; - }; - framebuffer-data { - nvidia,fb-bpp = <32>; /* bits per pixel */ - nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; - nvidia,fb-xres = <1280>; - nvidia,fb-yres = <720>; - }; + nvidia,out-type = <TEGRA_DC_OUT_HDMI>; + nvidia,fb-bpp = <32>; /* bits per pixel */ + nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>; + avdd_hdmi-supply = <&palmas_ldoln>; + avdd_hdmi_pll-supply = <&palmas_ldo1>; + vdd_hdmi_5v0-supply = <&vdd_hdmi>; }; - }; - + } diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt index 4a7add0de5fa..d8f946bad110 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-dsi.txt @@ -16,6 +16,7 @@ NVIDIA TEGRA124 Display Serial Interface 1.A) dsi panel node: dsi panel node must be contained in dsi parent node. This node represents dsi panel node. + It is possible to have multiple dsi panel nodes. Required properties - name: Can be arbitrary. @@ -34,11 +35,17 @@ NVIDIA TEGRA124 Display Serial Interface TEGRA_DSI_PIXEL_FORMAT_18BIT_P, TEGRA_DSI_PIXEL_FORMAT_18BIT_NP and TEGRA_DSI_PIXEL_FORMAT_24BIT_P, respectively. - nvidia,dsi-refresh-rate: Refresh rate. + - nvidia,dsi-rated-refresh-rate: dsi rated Refresh rate. - nvidia,dsi-virtual-channel: DSI virtual channel number. Write 0, 1, 2 and 3 for TEGRA_DSI_VIRTUAL_CHANNEL_0, TEGRA_DSI_VIRTUAL_CHANNEL_1, TEGRA_DSI_VIRTUAL_CHANNEL_2 and TEGRA_DSI_VIRTUAL_CHANNEL_3, respectively. - nvidia,dsi-instance: Should be 0 or 1: DSI controller or DSIB controller. - nvidia,dsi-panel-reset: Indicate if dsi output device requires hardware reset or not. + - nvidia,dsi-te-polarity-low: 1 if dsi panel te polarity is low. - nvidia,dsi-power-saving-suspend: With enabled, set dsi controller ultra low power mode in suspend. + - nvidia,dsi-lp00-pre-panel-wakeup: With 1, maintain dsi lp-00 before panel wake-up + - nvidia,dsi-bl-name: Backlight device name. It may be same with nvidia,bl-device-name. + - nvidia,dsi-suspend-aggr: DSI suspend aggressiveness. DSI_HOST_SUSPEND_LV2, DSI_HOST_SUSPEND_LV1, + DSI_HOST_SUSPEND_LV0 or DSI_NO_SUSPEND can be set. - nvidia,dsi-ulpm-not-support: With enabled, do not enter dsi ulpm mode. - nvidia,dsi-video-data-type: The DSI operates in two transmission modes: video and host/command. Write 0, 1 for TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, respectively. @@ -72,48 +79,330 @@ NVIDIA TEGRA124 Display Serial Interface - nvidia,dsi-phy-tasure: dsi phy timing, t_tasure_ns. - nvidia,dsi-phy-tago: dsi phy timing, t_tago_ns. + - Child nodes represent node of modes, output settings, + smart dimmer settings, color management unit settings. + +1.A.i) NVIDIA Display Controller Modes + This must be contained in dsi panel parent node. This contains supported modes. + + Required properties: + - name: Should be "display-timings" + + - Child nodes represent modes. Several modes can be prepared. + +1.A.i.x) NVIDIA Display Controller Mode timing + This must be contained in display-timings parent node. This contains mode settings, including + display timings. For hdmi out-type case, display-timings properties are only valid in case of + hdmi fb console mode. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - hactive, vactive: display resolution. + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels. + - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines. + - clock-frequency: display clock in Hz. + - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC + with respect to H reference point. + - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC + with respect to V reference point. + +1.A.j) NVIDIA Display Default Output Settings + This must be contained in dsi panel parent node. This is default output settings. + + Required properties: + - name: Should be "disp-default-out". + - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. + - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. + - nvidia,out-flags: One item or an array of several tuples items can be chosen. + List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, + TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, + TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, + TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. + If several items are written, bitwise OR is operated for them, internally. + - nvidia,out-parent-clk: Parent clk for display controller. + - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. + - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. + - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or + TEGRA_DC_ORDER_BLUE_RED. + - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for + BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, + BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, + and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. + For hdmi out-type case, depth selection is only valid for hdmi fb console mode, + otherwise, BASE_COLOR_SIZE888 is chosen as a default. + - nvidia,out-xres: Visible resolution for width. + - nvidia,out-yres: Visible resolution for height. + +1.A.k) NVIDIA Display Controller Smart Dimmer Settings + This must be contained in dsi panel parent node. This is smart dimmer settings. + + Required properties: + - name: Should be "smartdimmer". + - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control + signal directly. + - nvidia,hw-update-delay: It determines the delay of the update of the hardware + enhancement value (K) that is applied to the pixels. + - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. + 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment + of -1, indicates automatic based on aggressiveness. + - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. + - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. + - nvidia,phase-in-adjustments: Software backlight phase-in + - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) + rather than computed from nvidia,aggressiveness. + - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of + aggressiveness. + - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) + to a rectangular subset of display. + - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels + above nvidia,soft-clipping-threshold level to avoid saturation. + - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. + - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to + nvidia,smooth-k-incr. + - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed + at most by smooth-k-incr per frame. + - nvidia,coeff: Luminance calculation coefficients used to convert the red green and + blue color components into a luminance value. The conversion is performed according to + the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. + Need to write blue, green, red coefficient for luminance calculation in sequence. + - nvidia,fc: Flicker control that prevents rapid and frequent changes + in the enhancement value. Need to write time_limit, threshold in sequence. + - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to + write time_constant for the response curve and step that determines the instantaneous + portion of the target value of enhancement that is applied: <time_constant, step>. + - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve + defines how the backlight output changes with respect to the control input. The 17th point + is defined to be the maximum value. + - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k + for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). + There are nine entries in total. + - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. + - nvidia,bl-device-name: Backlight device name. + +1.A.l) NVIDIA Display Controller Color Management Unit Settings + This must be contained in dsi parent node. This is color management unit settings. + + Required properties: + - name: Should be "cmu". + - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. + - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + Example + host1x { dsi { + status = "okay"; compatible = "nvidia,tegra124-dsi"; reg = <0x54300000 0x00040000>, <0x54400000 0x00040000>; - status = "okay"; - nvidia,dsi-controller-vs = <1>; - panel-l-wxga-7 { + nvidia,dsi-controller-vs = <DSI_VS_1>; + panel-p-wuxga-10-1 { status = "okay"; - compatible = "lg,wxga-7"; - nvidia,dsi-instance = <0>; + compatible = "p,wuxga-10-1"; + nvidia,dsi-instance = <DSI_INSTANCE_0>; nvidia,dsi-n-data-lanes = <4>; - nvidia,dsi-pixel-format = <3>; + nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>; nvidia,dsi-refresh-rate = <60>; - nvidia,dsi-video-data-type = <0>; - nvidia,dsi-video-clock-mode = <0>; - nvidia,dsi-video-burst-mode = <0>; - nvidia,dsi-virtual-channel = <0>; - nvidia,dsi-power-saving-suspend = <1>; - nvidia,dsi-phy-datzero = <270>; - nvidia,dsi-phy-hsprepare = <30>; - nvidia,dsi-phy-clkzero = <330>; - nvidia,dsi-phy-clkprepare = <27>; - nvidia,dsi-init-cmd = <0x0 0x15 0x01 0x0 0x0>, - <1 20>, - <0x0 0x15 0xae 0x0b 0x0>, - <0x0 0x15 0xee 0xea 0x0>, - <0x0 0x15 0xef 0x5f 0x0>, - <0x0 0x15 0xf2 0x68 0x0>, - <0x0 0x15 0xee 0x0 0x0>, - <0x0 0x15 0xef 0x0 0x0>; - nvidia,dsi-n-init-cmd = <8>; - nvidia,dsi-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, - <1 160>; - nvidia,dsi-n-suspend-cmd = <2>; - nvidia,dsi-late-resume-cmd = <0x0 0x15 0x10 0x0 0x0>, - <1 120>; - nvidia,dsi-n-late-resume-cmd = <2>; - nvidia,dsi-early-suspend-cmd = <0x0 0x15 0x11 0x0 0x0>, - <1 160>; - nvidia,dsi-n-early-suspend-cmd = <2>; + nvidia,dsi-video-data-type = <TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE>; + nvidia,dsi-video-clock-mode = <TEGRA_DSI_VIDEO_CLOCK_TX_ONLY>; + nvidia,dsi-video-burst-mode = <TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END>; + nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>; + nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>; + nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>; + nvidia,dsi-panel-bl-pwm-gpio = <&gpio TEGRA_GPIO(H, 1) 0>; /* PH1 */ + nvidia,dsi-pkt-seq = + <CMD_VS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_VE LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>, + <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>; + disp-default-out { + nvidia,out-width = <217>; + nvidia,out-height = <135>; + nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>; + nvidia,out-parent-clk = "pll_d_out0"; + nvidia,out-xres = <1920>; + nvidia,out-yres = <1200>; + }; + display-timings { + 1920x1200-32 { + clock-frequency = <154700000>; + hactive = <1920>; + vactive = <1200>; + hfront-porch = <120>; + hback-porch = <32>; + hsync-len = <16>; + vfront-porch = <17>; + vback-porch = <16>; + vsync-len = <2>; + nvidia,h-ref-to-sync = <4>; + nvidia,v-ref-to-sync = <1>; + }; + }; + smartdimmer { + status = "okay"; + nvidia,use-auto-pwm = <0>; + nvidia,hw-update-delay = <0>; + nvidia,bin-width = <0xffffffff>; + nvidia,aggressiveness = <5>; + nvidia,use-vid-luma = <0>; + nvidia,phase-in-settings = <0>; + nvidia,phase-in-adjustments = <0>; + nvidia,k-limit-enable = <1>; + nvidia,k-limit = <200>; + nvidia,sd-window-enable = <0>; + nvidia,soft-clipping-enable= <1>; + nvidia,soft-clipping-threshold = <128>; + nvidia,smooth-k-enable = <1>; + nvidia,smooth-k-incr = <4>; + nvidia,coeff = <5 9 2>; + nvidia,fc = <0 0>; + nvidia,blp = <1024 255>; + nvidia,bltf = <57 65 73 82 + 92 103 114 125 + 138 150 164 178 + 193 208 224 241>; + nvidia,lut = <255 255 255 + 199 199 199 + 153 153 153 + 116 116 116 + 85 85 85 + 59 59 59 + 36 36 36 + 17 17 17 + 0 0 0>; + nvidia,use-vpulse2 = <1>; + nvidia,bl-device-name = "pwm-backlight"; + }; + cmu { + nvidia,cmu-csc = < 0x138 0x3ba 0x00d + 0x3f5 0x120 0x3e6 + 0x3fe 0x3f8 0x0e9 >; + nvidia,cmu-lut2 = < 0 1 2 3 4 5 6 6 + 7 8 9 10 11 11 12 13 + 13 14 15 15 16 17 17 18 + 18 19 19 20 20 21 21 22 + 22 23 23 23 24 24 24 25 + 25 25 26 26 26 27 27 27 + 28 28 28 28 29 29 29 29 + 30 30 30 30 31 31 31 31 + 32 32 32 32 33 33 33 33 + 34 34 34 35 35 35 35 36 + 36 36 37 37 37 37 38 38 + 38 39 39 39 39 40 40 40 + 41 41 41 41 42 42 42 43 + 43 43 43 44 44 44 45 45 + 45 45 46 46 46 46 47 47 + 47 47 48 48 48 48 49 49 + 49 49 50 50 50 50 50 51 + 51 51 51 52 52 52 52 52 + 53 53 53 53 53 53 54 54 + 54 54 54 55 55 55 55 55 + 55 56 56 56 56 56 56 57 + 57 57 57 57 57 57 58 58 + 58 58 58 58 59 59 59 59 + 59 59 59 60 60 60 60 60 + 60 60 61 61 61 61 61 61 + 61 62 62 62 62 62 62 62 + 63 63 63 63 63 63 63 64 + 64 64 64 64 64 64 65 65 + 65 65 65 65 66 66 66 66 + 66 66 66 67 67 67 67 67 + 67 68 68 68 68 68 68 69 + 69 69 69 69 69 70 70 70 + 70 70 70 71 71 71 71 71 + 71 72 72 72 72 72 72 73 + 73 73 73 73 73 74 74 74 + 74 74 74 74 75 75 75 75 + 75 75 76 76 76 76 76 76 + 77 77 77 77 77 77 77 78 + 78 78 78 78 78 79 79 79 + 79 79 79 79 80 80 80 80 + 80 80 80 80 81 81 81 81 + 81 81 81 82 82 82 82 82 + 82 82 82 83 83 83 83 83 + 83 83 83 83 84 84 84 84 + 84 84 84 84 85 85 85 85 + 85 85 85 85 85 85 86 86 + 86 86 86 86 86 86 86 86 + 87 87 87 87 87 87 87 87 + 87 87 88 88 88 88 88 88 + 88 88 88 88 88 88 89 89 + 89 89 89 89 89 89 89 89 + 89 89 90 90 90 90 90 90 + 90 90 90 90 90 90 91 91 + 91 91 91 91 91 91 91 91 + 91 91 91 92 92 92 92 92 + 92 92 92 92 92 92 92 92 + 93 93 93 93 93 93 93 93 + 93 93 93 93 93 93 94 94 + 94 94 94 94 94 94 94 94 + 94 94 94 94 95 95 95 95 + 95 95 95 95 95 95 95 95 + 95 96 96 96 96 96 96 96 + 96 96 96 96 96 96 97 97 + 97 97 97 97 97 97 97 97 + 98 99 99 100 101 101 102 103 + 103 104 105 105 106 107 107 108 + 109 110 110 111 112 112 113 114 + 114 115 115 116 117 117 118 119 + 119 120 120 121 121 122 123 123 + 124 124 125 125 126 126 127 128 + 128 129 129 130 130 131 131 132 + 132 133 133 134 134 135 135 136 + 136 137 138 138 139 139 140 140 + 141 141 142 142 143 143 144 144 + 144 145 145 146 146 147 147 148 + 148 149 149 150 150 151 151 152 + 152 153 153 153 154 154 155 155 + 156 156 157 157 157 158 158 159 + 159 160 160 160 161 161 162 162 + 162 163 163 164 164 164 165 165 + 165 166 166 167 167 167 168 168 + 168 169 169 169 170 170 171 171 + 171 172 172 172 173 173 173 174 + 174 174 175 175 175 176 176 176 + 177 177 177 178 178 178 179 179 + 179 180 180 180 181 181 181 182 + 182 182 183 183 183 184 184 184 + 185 185 185 185 186 186 186 187 + 187 187 188 188 188 189 189 189 + 190 190 190 191 191 191 191 192 + 192 192 193 193 193 194 194 194 + 195 195 195 195 196 196 196 197 + 197 197 198 198 198 199 199 199 + 199 200 200 200 201 201 201 202 + 202 202 203 203 203 203 204 204 + 204 205 205 205 206 206 206 207 + 207 207 208 208 208 208 209 209 + 209 210 210 210 211 211 211 212 + 212 212 213 213 213 214 214 214 + 215 215 215 215 216 216 216 217 + 217 217 218 218 218 219 219 219 + 220 220 220 220 221 221 221 222 + 222 222 222 223 223 223 224 224 + 224 224 225 225 225 226 226 226 + 226 227 227 227 227 228 228 228 + 229 229 229 229 230 230 230 230 + 230 231 231 231 231 232 232 232 + 232 233 233 233 233 234 234 234 + 234 234 235 235 235 235 236 236 + 236 236 236 237 237 237 237 238 + 238 238 238 238 239 239 239 239 + 239 240 240 240 240 240 241 241 + 241 241 241 242 242 242 242 243 + 243 243 243 243 244 244 244 244 + 244 245 245 245 245 245 246 246 + 246 246 246 247 247 247 247 248 + 248 248 248 248 249 249 249 249 + 250 250 250 250 251 251 251 251 + 251 252 252 252 253 253 253 253 + 254 254 254 254 255 255 255 255 >; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt index 8613c36a9be3..4cee05b19ebb 100644 --- a/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt +++ b/Documentation/devicetree/bindings/video/nvidia,tegra124-hdmi.txt @@ -19,16 +19,133 @@ NVIDIA TEGRA124 High Definition Multimedia Interface which does only set DDC_SDA and DDC_SCL pull downs to be active when hotplug is detected, otherwise keep them disabled. - 1.B) NVIDIA HDMI TMDS configurations - This must be contained in hdmi parent node. This includes tmds configurations. + 1.A) The hdmi-display node: + hdmi-display must be contained in hdmi parent node. This node represents hdmi display node. + + Required properties + - name: hdmi-display + + - Child nodes represent tmds configurations, node of modes, output settings, + smart dimmer settings, color management unit settings. + + 1.A.i) NVIDIA Display Controller Modes + This must be contained in hdmi-display parent node. This contains supported modes. Required properties: - - name: Should be "nvidia,out-tmds-cfg" + - name: Should be "display-timings" + + - Child nodes represent modes. Several modes can be prepared. + + 1.A.i.x) NVIDIA Display Controller Mode timing + This must be contained in display-timings parent node. This contains mode settings, including + display timings. For hdmi out-type case, display-timings properties are only valid in case of + hdmi fb console mode. + + Required properties: + - name: Can be arbitrary, but each sibling node should have unique name. + - hactive, vactive: display resolution. + - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters + in pixels. + - vfront-porch, vback-porch, vsync-len: vertical display timing parameters in + lines. + - clock-frequency: display clock in Hz. + - nvidia,h-ref-to-sync: H reference to HSYNC. This specifies the start position of HSYNC + with respect to H reference point. + - nvidia,v-ref-to-sync: V reference to VSYNC. This specifies the start position of VSYNC + with respect to V reference point. + + 1.A.j) NVIDIA Display Default Output Settings + This must be contained in hdmi-display parent node. This is default output settings. + + Required properties: + - name: Should be "disp-default-out". + - nvidia,out-width: Width in struct fb_var_screeninfo. width of picture in mm. + - nvidia,out-height: Height in struct fb_var_screeninfo. height of picture in mm. + - nvidia,out-flags: One item or an array of several tuples items can be chosen. + List of items is TEGRA_DC_OUT_HOTPLUG_HIGH, TEGRA_DC_OUT_HOTPLUG_LOW, + TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND, TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON, + TEGRA_DC_OUT_CONTINUOUS_MODE, TEGRA_DC_OUT_ONE_SHOT_MODE, + TEGRA_DC_OUT_N_SHOT_MODE, TEGRA_DC_OUT_ONE_SHOT_LP_MODE, + TEGRA_DC_OUT_INITIALIZED_MODE and TEGRA_DC_OUT_HOTPLUG_WAKE_LP0. + If several items are written, bitwise OR is operated for them, internally. + - nvidia,out-parent-clk: Parent clk for display controller. + - nvidia,out-max-pixclk: Maximum pixel clock in pico-seconds. + - nvidia,out-align: Display data alignment. Should be TEGRA_DC_ALIGN_MSB or TEGRA_DC_ALIGN_LSB. + - nvidia,out-order: Display data order. Should be TEGRA_DC_ORDER_RED_BLUE or + TEGRA_DC_ORDER_BLUE_RED. + - nvidia,out-depth: Display base color size. 3, 6, 8, 9, 12, 15, 16, 18 and 24 for + BASE_COLOR_SIZE111, BASE_COLOR_SIZE222, BASE_COLOR_SIZE332, BASE_COLOR_SIZE333, + BASE_COLOR_SIZE444, BASE_COLOR_SIZE555, BASE_COLOR_SIZE565, BASE_COLOR_SIZE666, + and BASE_COLOR_SIZE888, respectively. In default, BASE_COLOR_SIZE888 is chosen. + For hdmi out-type case, depth selection is only valid for hdmi fb console mode, + otherwise, BASE_COLOR_SIZE888 is chosen as a default. + - nvidia,out-xres: Visible resolution for width. + - nvidia,out-yres: Visible resolution for height. + + 1.A.k) NVIDIA Display Controller Smart Dimmer Settings + This must be contained in hdmi-display parent node. This is smart dimmer settings. + + Required properties: + - name: Should be "smartdimmer". + - nvidia,use-auto-pwm: With enabled, hardware adjust the backlight PWM control + signal directly. + - nvidia,hw-update-delay: It determines the delay of the update of the hardware + enhancement value (K) that is applied to the pixels. + - nvidia,bin-width: It is the width of the histogram bins, in quantisation level. + 0xffffffff, 1, 2, 4 or 8 can be written, 0xffffffff, which means 2's compliment + of -1, indicates automatic based on aggressiveness. + - nvidia,aggressiveness: The aggressiveness level of the smart dimmer algorithm. + - nvidia,use-vid-luma: With enabled, it uses video luminance control of luminance. + - nvidia,phase-in-adjustments: Software backlight phase-in + - nvidia,k-limit-enable: When enabled, Max.K is taken from K_LIMIT register (nvidia,k-limit) + rather than computed from nvidia,aggressiveness. + - nvidia,k-limit: When nvidia,k-limit-enable is enabled, limits raw K independently of + aggressiveness. + - nvidia,sd-window-enable: When enabled, constrain histogram (and therefore backlight) + to a rectangular subset of display. + - nvidia,soft-clipping-enable: When enabled, enhancement gain (K) is reduced for pixels + above nvidia,soft-clipping-threshold level to avoid saturation. + - nvidia,soft-clipping-threshold: Threshold at which pixel enhancement gain is reduced. + - nvidia,smooth-k-enable: When enabled, max raw K change per frame is limited to + nvidia,smooth-k-incr. + - nvidia,smooth-k-incr: When nvidia,smooth-k-enable is enabled, the raw K is changed + at most by smooth-k-incr per frame. + - nvidia,coeff: Luminance calculation coefficients used to convert the red green and + blue color components into a luminance value. The conversion is performed according to + the following equation: Luminance = (R*R_COEFF + G*G_COEFF + B*B_COEFF) >> 4. + Need to write blue, green, red coefficient for luminance calculation in sequence. + - nvidia,fc: Flicker control that prevents rapid and frequent changes + in the enhancement value. Need to write time_limit, threshold in sequence. + - nvidia,blp: Defines the parameters for the backlight temporal response model. Need to + write time_constant for the response curve and step that determines the instantaneous + portion of the target value of enhancement that is applied: <time_constant, step>. + - nvidia,bltf: Backlight transfer function. Each points on the transfer function curve + defines how the backlight output changes with respect to the control input. The 17th point + is defined to be the maximum value. + - nvidia,lut: Enhancement value (K) look up table. each LUT entry contains the value of k + for each of the three color components (R_LUT, G_LUT, B_LUT in sequence). + There are nine entries in total. + - nvidia,use-vpulse2: With enabled, run histogram on vpulse2 rather than vsync. + - nvidia,bl-device-name: Backlight device name. + + 1.A.l) NVIDIA Display Controller Color Management Unit Settings + This must be contained in hdmi-display node. This is color management unit settings. + + Required properties: + - name: Should be "cmu". + - nvidia,cmu-csc: CMU color space conversion matrix. It is 3X3 matrix. + - nvidia,cmu-lut2: CMU LUT2. Should be 960 u8 arrays. + + 1.A.m) NVIDIA HDMI TMDS configurations + This must be contained in hdmi-display parent node. This includes tmds configurations. + + Required properties: + - name: Should be "tmds-config" - Child nodes represent tmds configurations. Several configurations can be prepared. - 1.B.i) NVIDIA HDMI TMDS configuration - This must be contained in nvidia,out-tmds-cfg parent node. This includes tmds configuration. + 1.A.m.x) NVIDIA HDMI TMDS configuration + This must be contained in tmds-config parent node. This includes tmds configuration. Required properties: - name: Can be arbitrary, but each sibling node should have unique name. @@ -46,13 +163,75 @@ NVIDIA TEGRA124 High Definition Multimedia Interface - pad-ctls0-setting: HDMI_NV_PDISP_SOR_PAD_CTLS0_0 register or mask. Example + host1x { hdmi { + status = "okay"; compatible = "nvidia,tegra124-hdmi"; reg = <0x54280000 0x00040000>; interrupts = <0 75 0x04>; - status = "okay"; nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio 111 1>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 1>; /* PN7 */ + hdmi-display { + status = "okay"; + disp-default-out { + nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_HIGH>; + nvidia,out-parent-clk = "pll_d2"; + nvidia,out-max-pixclk = <3367>; /* KHZ2PICOS(297000) */ + nvidia,out-align = <TEGRA_DC_ALIGN_MSB>; + nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>; + nvidia,out-xres = <1920>; + nvidia,out-yres = <1080>; + }; + tmds-config { + tmds-cfg@0 { + version = <1 0>; + pclk = <27000000>; + pll0 = <0x01003010>; + pll1 = <0x00301b00>; + pe-current = <0x00000000>; + drive-current = <0x1f1f1f1f>; + peak-current = <0x03030303>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000400>; + }; + tmds-cfg@1 { + version = <1 0>; + pclk = <74250000>; + pll0 = <0x01003110>; + pll1 = <0x00301500>; + pe-current = <0x00000000>; + drive-current = <0x2c2c2c2c>; + peak-current = <0x07070707>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000400>; + }; + tmds-cfg@2 { + version = <1 0>; + pclk = <148500000>; + pll0 = <0x01003310>; + pll1 = <0x00301500>; + pe-current = <0x00000000>; + drive-current = <0x33333333>; + peak-current = <0x0c0c0c0c>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000400>; + }; + tmds-cfg@3 { + version = <1 0>; + pclk = <0x7fffffff>; + pll0 = <0x01003f10>; + pll1 = <0x00300f00>; + pe-current = <0x00000000>; + drive-current = <0x37373737>; + peak-current = <0x17171717>; + pad-ctls0-mask = <0xfffff0ff>; + pad-ctls0-setting = <0x00000600>; + }; + }; + }; }; }; + hdmi_ddc: i2c@7000c700 { + clock-frequency = <100000>; + }; diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 5cc2592a8d41..12252eff9ef7 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -2970,6 +2970,7 @@ static int tegra_dc_probe(struct platform_device *ndev) dc->base = base; dc->irq = irq; dc->ndev = ndev; + dc->fb_mem = fb_mem; if (!np) dc->pdata = ndev->dev.platform_data; diff --git a/drivers/video/tegra/dc/of_dc.c b/drivers/video/tegra/dc/of_dc.c index 7785d58502b3..45f45c7481a8 100644 --- a/drivers/video/tegra/dc/of_dc.c +++ b/drivers/video/tegra/dc/of_dc.c @@ -69,46 +69,8 @@ #define OF_DC_LOG(fmt, args...) #endif -#define DC_GEN_NODE "/host1x/dc@" #define DSI_NODE "/host1x/dsi" #define HDMI_NODE "/host1x/hdmi" -#define STRING_ADDR(x) #x -#define DC0_BASE_ADDR STRING_ADDR(54200000) -#define DC1_BASE_ADDR STRING_ADDR(54240000) -#define DEFAULT_OUT "/dc-default-out" -#define DISP_TIMINGS "/display-timings" -#define SMARTDIMMER "/smartdimmer" -#define CMU "/cmu" -#define FRAMEBUFFER_DATA "/framebuffer-data" -#define OUT_TMDS_CFG "/nvidia,out-tmds-cfg" - -#define DC0_DEFAULT_OUT \ - (DC_GEN_NODE DC0_BASE_ADDR DEFAULT_OUT) -#define DC1_DEFAULT_OUT \ - (DC_GEN_NODE DC1_BASE_ADDR DEFAULT_OUT) - -#define DC0_DISP_TIMINGS \ - (DC_GEN_NODE DC0_BASE_ADDR DISP_TIMINGS) -#define DC1_DISP_TIMINGS \ - (DC_GEN_NODE DC1_BASE_ADDR DISP_TIMINGS) - -#define DC0_SMARTDIMMER \ - (DC_GEN_NODE DC0_BASE_ADDR SMARTDIMMER) -#define DC1_SMARTDIMMER \ - (DC_GEN_NODE DC1_BASE_ADDR SMARTDIMMER) - -#define DC0_CMU \ - (DC_GEN_NODE DC0_BASE_ADDR CMU) -#define DC1_CMU \ - (DC_GEN_NODE DC1_BASE_ADDR CMU) - -#define DC0_FRAMEBUFFER_DATA \ - (DC_GEN_NODE DC0_BASE_ADDR FRAMEBUFFER_DATA) -#define DC1_FRAMEBUFFER_DATA \ - (DC_GEN_NODE DC1_BASE_ADDR FRAMEBUFFER_DATA) - -#define TMDS_CFG_NODE \ - (HDMI_NODE OUT_TMDS_CFG) static struct regulator *of_hdmi_vddio; static struct regulator *of_hdmi_reg; @@ -291,29 +253,25 @@ static bool is_dc_default_out_flag(u32 flag) return false; } -static int parse_dc_default_out(struct platform_device *ndev, - struct device_node *np, struct tegra_dc_out *default_out) +static int parse_disp_default_out(struct platform_device *ndev, + struct device_node *np, + struct tegra_dc_out *default_out, + struct tegra_fb_data *fb) { - int err; u32 temp; int hotplug_gpio = 0; enum of_gpio_flags flags; struct device_node *ddc; struct device_node *np_hdmi = of_find_node_by_path(HDMI_NODE); - struct device_node *tmds_np = NULL; - struct device_node *entry = NULL; - u8 *addr; struct property *prop; const __be32 *p; u32 u; const char *temp_str0; - err = parse_dc_out_type(np, default_out); - if (err) { - pr_err("parse_dc_out_type err\n"); - return err; - } + /* + * construct default_out + */ if (!of_property_read_u32(np, "nvidia,out-width", &temp)) { default_out->width = (unsigned) temp; OF_DC_LOG("out_width %d\n", default_out->width); @@ -322,10 +280,6 @@ static int parse_dc_default_out(struct platform_device *ndev, default_out->height = (unsigned) temp; OF_DC_LOG("out_height %d\n", default_out->height); } - if (!of_property_read_u32(np, "nvidia,out-rotation", &temp)) { - default_out->rotation = (unsigned) temp; - OF_DC_LOG("out_rotation %d\n", default_out->rotation); - } if (np_hdmi && of_device_is_available(np_hdmi) && (default_out->type == TEGRA_DC_OUT_HDMI)) { int id; @@ -350,6 +304,7 @@ static int parse_dc_default_out(struct platform_device *ndev, if (hotplug_gpio != 0) default_out->hotplug_gpio = hotplug_gpio; } + if (!of_property_read_u32(np, "nvidia,out-max-pixclk", &temp)) { default_out->max_pixclock = (unsigned)temp; OF_DC_LOG("%u max_pixclock in pico second unit\n", @@ -365,7 +320,6 @@ static int parse_dc_default_out(struct platform_device *ndev, } OF_DC_LOG("default_out flag %u\n", default_out->flags); - if (!of_property_read_u32(np, "nvidia,out-align", &temp)) { if (temp == TEGRA_DC_ALIGN_MSB) OF_DC_LOG("tegra dc align msb\n"); @@ -390,25 +344,78 @@ static int parse_dc_default_out(struct platform_device *ndev, default_out->order = (unsigned)temp; } - if (!of_property_read_string(np, "nvidia,out-parent-clk", &temp_str0)) { + if (!of_property_read_string(np, "nvidia,out-parent-clk", + &temp_str0)) { default_out->parent_clk = temp_str0; OF_DC_LOG("parent clk %s\n", default_out->parent_clk); } else { - goto fail_dc_default_out; + goto fail_disp_default_out; } + + if (default_out->type == TEGRA_DC_OUT_HDMI) { + default_out->depth = 0; +#ifdef CONFIG_FRAMEBUFFER_CONSOLE + if (!of_property_read_u32(np, + "nvidia,out-depth", &temp)) { + default_out->depth = (unsigned) temp; + OF_DC_LOG("out-depth for HDMI FB console %d\n", temp); + } +#endif + } else { + /* default_out->type == TEGRA_DC_OUT_DSI */ + if (!of_property_read_u32(np, + "nvidia,out-depth", &temp)) { + default_out->depth = (unsigned) temp; + OF_DC_LOG("out-depth for DSI display %d\n", temp); + } + } + + /* + * construct fb + */ + fb->win = 0; /* set fb->win to 0 in default */ + + if (!of_property_read_u32(np, "nvidia,out-xres", &temp)) { + fb->xres = (int)temp; + OF_DC_LOG("framebuffer xres %d\n", fb->xres); + } else { + goto fail_disp_default_out; + } + if (!of_property_read_u32(np, "nvidia,out-yres", &temp)) { + fb->yres = (int)temp; + OF_DC_LOG("framebuffer yres %d\n", fb->yres); + } else { + goto fail_disp_default_out; + } + + return 0; + +fail_disp_default_out: + pr_err("%s: a parse error\n", __func__); + return -EINVAL; +} + +int parse_tmds_config(struct platform_device *ndev, + struct device_node *np, struct tegra_dc_out *default_out) +{ + int err = 0; + u8 *addr; + struct device_node *tmds_np = NULL; + struct device_node *entry = NULL; + if (default_out->type == TEGRA_DC_OUT_HDMI) - tmds_np = of_find_node_by_path(TMDS_CFG_NODE); + tmds_np = of_get_child_by_name(np, "tmds-config"); if (!tmds_np) { - pr_info("%s: No nvidia,out-tmds-cfg\n", + pr_info("%s: No tmds-config node\n", __func__); } else { int tmds_set_count = of_get_child_count(tmds_np); if (!tmds_set_count) { pr_info("tmds node exists but no cfg!\n"); - goto success_dc_default_out; + goto success_tmds_config; } default_out->hdmi_out = devm_kzalloc(&ndev->dev, @@ -431,31 +438,14 @@ static int parse_dc_default_out(struct platform_device *ndev, for_each_child_of_node(tmds_np, entry) { err = parse_tmds(entry, addr); if (err) - goto fail_dc_default_out; + goto fail_tmds_config; addr += sizeof(struct tmds_config); } } - if (default_out->type == TEGRA_DC_OUT_HDMI) { - default_out->depth = 0; -#ifdef CONFIG_FRAMEBUFFER_CONSOLE - if (!of_property_read_u32(np, - "nvidia,out-depth", &temp)) { - default_out->depth = (unsigned) temp; - OF_DC_LOG("out-depth for HDMI FB console %d\n", temp); - } -#endif - } else { - /* default_out->type == TEGRA_DC_OUT_DSI */ - if (!of_property_read_u32(np, - "nvidia,out-depth", &temp)) { - default_out->depth = (unsigned) temp; - OF_DC_LOG("out-depth for DSI display %d\n", temp); - } - } -success_dc_default_out: +success_tmds_config: return 0; -fail_dc_default_out: +fail_tmds_config: pr_err("%s: a parse error\n", __func__); return -EINVAL; } @@ -783,53 +773,6 @@ static int parse_cmu_data(struct device_node *np, } #endif -static int parse_fb_info(struct device_node *np, struct tegra_fb_data *fb) -{ - u32 temp; - - /* - * set fb->win to 0 in default - */ - fb->win = 0; - - if (!of_property_read_u32(np, "nvidia,fb-bpp", &temp)) { - fb->bits_per_pixel = (int)temp; - OF_DC_LOG("fb bpp %d\n", fb->bits_per_pixel); - } else { - goto fail_fb_info; - } - - if (!of_property_read_u32(np, "nvidia,fb-flags", &temp)) { - if (temp == TEGRA_FB_FLIP_ON_PROBE) - OF_DC_LOG("fb flip on probe\n"); - else if (temp == 0) - OF_DC_LOG("do not flip fb on probe time\n"); - else { - pr_err("invalid fb_flags\n"); - return -EINVAL; - } - fb->flags = (unsigned long)temp; - } - - if (!of_property_read_u32(np, "nvidia,fb-xres", &temp)) { - fb->xres = (int)temp; - OF_DC_LOG("fb xres %d\n", fb->xres); - } else { - goto fail_fb_info; - } - if (!of_property_read_u32(np, "nvidia,fb-yres", &temp)) { - fb->yres = (int)temp; - OF_DC_LOG("fb yres %d\n", fb->yres); - } else { - goto fail_fb_info; - } - return 0; - -fail_fb_info: - pr_err("%s: a parse error\n", __func__); - return -EINVAL; -} - struct tegra_dsi_cmd *tegra_dsi_parse_cmd_dt(struct platform_device *ndev, const struct device_node *node, struct property *prop, @@ -951,21 +894,21 @@ static const u32 *tegra_dsi_parse_pkt_seq_dt(struct platform_device *ndev, return pkt_seq; } -int parse_dsi_settings(struct platform_device *ndev, - struct device_node *np_dsi, struct tegra_dc_platform_data *pdata) +struct device_node *parse_dsi_settings(struct platform_device *ndev, + struct device_node *np_dsi, + struct tegra_dc_platform_data *pdata) { u32 temp; - int err = 0; int dsi_te_gpio = 0; int bl_name_len = 0; - struct device_node *np_panel; struct tegra_dsi_out *dsi = pdata->default_out->dsi; + struct device_node *np_dsi_panel = NULL; - np_panel = tegra_panel_get_dt_node(pdata); + np_dsi_panel = tegra_panel_get_dt_node(pdata); - if (!np_panel) { + if (!np_dsi_panel) { pr_err("There is no valid panel node\n"); - return -EINVAL; + return NULL; } if (!of_property_read_u32(np_dsi, "nvidia,dsi-controller-vs", &temp)) { @@ -976,16 +919,16 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi controller vs DSI_VS_1\n"); else { pr_err("invalid dsi controller version\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-n-data-lanes", &temp)) { dsi->n_data_lanes = (u8)temp; OF_DC_LOG("n data lanes %d\n", dsi->n_data_lanes); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-video-burst-mode", &temp)) { dsi->video_burst_mode = (u8)temp; if (temp == TEGRA_DSI_VIDEO_NONE_BURST_MODE) @@ -1004,10 +947,10 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi video BURST_MODE_FASTEST_SPEED\n"); else { pr_err("invalid dsi video burst mode\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-pixel-format", &temp)) { dsi->pixel_format = (u8)temp; if (temp == TEGRA_DSI_PIXEL_FORMAT_16BIT_P) @@ -1020,21 +963,21 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi pixel format 24BIT_P\n"); else { pr_err("invalid dsi pixel format\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-refresh-rate", &temp)) { dsi->refresh_rate = (u8)temp; OF_DC_LOG("dsi refresh rate %d\n", dsi->refresh_rate); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-rated-refresh-rate", &temp)) { dsi->rated_refresh_rate = (u8)temp; OF_DC_LOG("dsi rated refresh rate %d\n", dsi->rated_refresh_rate); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-virtual-channel", &temp)) { dsi->virtual_channel = (u8)temp; if (temp == TEGRA_DSI_VIRTUAL_CHANNEL_0) @@ -1047,10 +990,10 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi virtual channel 3\n"); else { pr_err("invalid dsi virtual ch\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, "nvidia,dsi-instance", &temp)) { + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-instance", &temp)) { dsi->dsi_instance = (u8)temp; if (temp == DSI_INSTANCE_0) OF_DC_LOG("dsi instance 0\n"); @@ -1058,41 +1001,31 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi instance 1\n"); else { pr_err("invalid dsi instance\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, "nvidia,dsi-panel-reset", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-panel-reset", &temp)) { dsi->panel_reset = (u8)temp; OF_DC_LOG("dsi panel reset %d\n", dsi->panel_reset); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-te-polarity-low", &temp)) { dsi->te_polarity_low = (u8)temp; OF_DC_LOG("dsi panel te polarity low %d\n", dsi->te_polarity_low); } - if (!of_property_read_u32(np_panel, - "nvidia,dsi-power-saving-suspend", &temp)) { - dsi->power_saving_suspend = (u8)temp; - OF_DC_LOG("dsi panel power saving suspend %d\n", - dsi->power_saving_suspend); - } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-lp00-pre-panel-wakeup", &temp)) { dsi->lp00_pre_panel_wakeup = (u8)temp; OF_DC_LOG("dsi panel lp00 pre panel wakeup %d\n", dsi->lp00_pre_panel_wakeup); } - if (!of_property_read_u32(np_panel, - "nvidia,dsi-ulpm-not-supported", &temp)) { - dsi->ulpm_not_supported = (u8)temp; - OF_DC_LOG("dsi panel ulpm not supported %d\n", - dsi->ulpm_not_supported); - } - if (of_find_property(np_panel, "nvidia,dsi-bl-name", &bl_name_len)) { + if (of_find_property(np_dsi_panel, + "nvidia,dsi-bl-name", &bl_name_len)) { dsi->bl_name = devm_kzalloc(&ndev->dev, sizeof(u8) * bl_name_len, GFP_KERNEL); - if (!of_property_read_string(np_panel, + if (!of_property_read_string(np_dsi_panel, "nvidia,dsi-bl-name", (const char **)&dsi->bl_name)) OF_DC_LOG("dsi panel bl name %s\n", dsi->bl_name); @@ -1102,30 +1035,37 @@ int parse_dsi_settings(struct platform_device *ndev, } } - if (!of_property_read_u32(np_panel, "nvidia,dsi-ganged-type", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-ganged-type", &temp)) { dsi->ganged_type = (u8)temp; OF_DC_LOG("dsi ganged_type %d\n", dsi->ganged_type); } - dsi_te_gpio = of_get_named_gpio(np_panel, "nvidia,dsi-te-gpio", 0); + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-suspend-aggr", &temp)) { + dsi->suspend_aggr = (u8)temp; + OF_DC_LOG("dsi suspend_aggr %d\n", dsi->suspend_aggr); + } + + dsi_te_gpio = of_get_named_gpio(np_dsi_panel, "nvidia,dsi-te-gpio", 0); if (gpio_is_valid(dsi_te_gpio)) { dsi->te_gpio = dsi_te_gpio; OF_DC_LOG("dsi te_gpio %d\n", dsi_te_gpio); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-power-saving-suspend", &temp)) { dsi->power_saving_suspend = (bool)temp; OF_DC_LOG("dsi power saving suspend %d\n", dsi->power_saving_suspend); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-ulpm-not-support", &temp)) { dsi->ulpm_not_supported = (bool)temp; OF_DC_LOG("dsi ulpm_not_supported %d\n", dsi->ulpm_not_supported); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-video-data-type", &temp)) { dsi->video_data_type = (u8)temp; if (temp == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) @@ -1134,10 +1074,10 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi video type COMMAND_MODE\n"); else { pr_err("invalid dsi video data type\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-video-clock-mode", &temp)) { dsi->video_clock_mode = (u8)temp; if (temp == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) @@ -1146,192 +1086,201 @@ int parse_dsi_settings(struct platform_device *ndev, OF_DC_LOG("dsi video clock mode TX_ONLY\n"); else { pr_err("invalid dsi video clk mode\n"); - return -EINVAL; + return NULL; } } - if (!of_property_read_u32(np_panel, "nvidia,dsi-n-init-cmd", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-n-init-cmd", &temp)) { dsi->n_init_cmd = (u16)temp; OF_DC_LOG("dsi n_init_cmd %d\n", dsi->n_init_cmd); } dsi->dsi_init_cmd = - tegra_dsi_parse_cmd_dt(ndev, np_panel, - of_find_property(np_panel, + tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel, + of_find_property(np_dsi_panel, "nvidia,dsi-init-cmd", NULL), dsi->n_init_cmd); if (dsi->n_init_cmd && IS_ERR_OR_NULL(dsi->dsi_init_cmd)) { dev_err(&ndev->dev, "dsi: copy init cmd from dt failed\n"); - err = PTR_ERR(dsi->dsi_init_cmd); - return err; + return NULL; }; - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-n-suspend-cmd", &temp)) { dsi->n_suspend_cmd = (u16)temp; OF_DC_LOG("dsi n_suspend_cmd %d\n", dsi->n_suspend_cmd); } dsi->dsi_suspend_cmd = - tegra_dsi_parse_cmd_dt(ndev, np_panel, - of_find_property(np_panel, + tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel, + of_find_property(np_dsi_panel, "nvidia,dsi-suspend-cmd", NULL), dsi->n_suspend_cmd); if (dsi->n_suspend_cmd && IS_ERR_OR_NULL(dsi->dsi_suspend_cmd)) { dev_err(&ndev->dev, "dsi: copy suspend cmd from dt failed\n"); - err = PTR_ERR(dsi->dsi_suspend_cmd); - return err; + return NULL; }; - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-n-early-suspend-cmd", &temp)) { dsi->n_early_suspend_cmd = (u16)temp; OF_DC_LOG("dsi n_early_suspend_cmd %d\n", dsi->n_early_suspend_cmd); } dsi->dsi_early_suspend_cmd = - tegra_dsi_parse_cmd_dt(ndev, np_panel, - of_find_property(np_panel, + tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel, + of_find_property(np_dsi_panel, "nvidia,dsi-early-suspend-cmd", NULL), dsi->n_early_suspend_cmd); if (dsi->n_early_suspend_cmd && IS_ERR_OR_NULL(dsi->dsi_early_suspend_cmd)) { dev_err(&ndev->dev, "dsi: copy early suspend cmd from dt failed\n"); - err = PTR_ERR(dsi->dsi_early_suspend_cmd); - return err; + return NULL; }; - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-n-late-resume-cmd", &temp)) { dsi->n_late_resume_cmd = (u16)temp; OF_DC_LOG("dsi n_late_resume_cmd %d\n", dsi->n_late_resume_cmd); } dsi->dsi_late_resume_cmd = - tegra_dsi_parse_cmd_dt(ndev, np_panel, - of_find_property(np_panel, + tegra_dsi_parse_cmd_dt(ndev, np_dsi_panel, + of_find_property(np_dsi_panel, "nvidia,dsi-late-resume-cmd", NULL), dsi->n_late_resume_cmd); if (dsi->n_late_resume_cmd && IS_ERR_OR_NULL(dsi->dsi_late_resume_cmd)) { dev_err(&ndev->dev, "dsi: copy late resume cmd from dt failed\n"); - err = PTR_ERR(dsi->dsi_late_resume_cmd); - return err; + return NULL; }; dsi->pkt_seq = - tegra_dsi_parse_pkt_seq_dt(ndev, np_panel, - of_find_property(np_panel, + tegra_dsi_parse_pkt_seq_dt(ndev, np_dsi_panel, + of_find_property(np_dsi_panel, "nvidia,dsi-pkt-seq", NULL)); if (IS_ERR(dsi->pkt_seq)) { dev_err(&ndev->dev, "dsi pkt seq from dt fail\n"); - return PTR_ERR(dsi->pkt_seq); + return NULL; } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-hsdexit", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-hsdexit", &temp)) { dsi->phy_timing.t_hsdexit_ns = (u16)temp; OF_DC_LOG("phy t_hsdexit_ns %d\n", dsi->phy_timing.t_hsdexit_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-hstrail", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-hstrail", &temp)) { dsi->phy_timing.t_hstrail_ns = (u16)temp; OF_DC_LOG("phy t_hstrail_ns %d\n", dsi->phy_timing.t_hstrail_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-datzero", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-datzero", &temp)) { dsi->phy_timing.t_datzero_ns = (u16)temp; OF_DC_LOG("phy t_datzero_ns %d\n", dsi->phy_timing.t_datzero_ns); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-phy-hsprepare", &temp)) { dsi->phy_timing.t_hsprepare_ns = (u16)temp; OF_DC_LOG("phy t_hsprepare_ns %d\n", dsi->phy_timing.t_hsprepare_ns); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-phy-clktrail", &temp)) { dsi->phy_timing.t_clktrail_ns = (u16)temp; OF_DC_LOG("phy t_clktrail_ns %d\n", dsi->phy_timing.t_clktrail_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-clkpost", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-clkpost", &temp)) { dsi->phy_timing.t_clkpost_ns = (u16)temp; OF_DC_LOG("phy t_clkpost_ns %d\n", dsi->phy_timing.t_clkpost_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-clkzero", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-clkzero", &temp)) { dsi->phy_timing.t_clkzero_ns = (u16)temp; OF_DC_LOG("phy t_clkzero_ns %d\n", dsi->phy_timing.t_clkzero_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-tlpx", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-tlpx", &temp)) { dsi->phy_timing.t_tlpx_ns = (u16)temp; OF_DC_LOG("phy t_tlpx_ns %d\n", dsi->phy_timing.t_tlpx_ns); } - if (!of_property_read_u32(np_panel, + if (!of_property_read_u32(np_dsi_panel, "nvidia,dsi-phy-clkprepare", &temp)) { dsi->phy_timing.t_clkprepare_ns = (u16)temp; OF_DC_LOG("phy t_clkprepare_ns %d\n", dsi->phy_timing.t_clkprepare_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-clkpre", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-clkpre", &temp)) { dsi->phy_timing.t_clkpre_ns = (u16)temp; OF_DC_LOG("phy t_clkpre_ns %d\n", dsi->phy_timing.t_clkpre_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-wakeup", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-wakeup", &temp)) { dsi->phy_timing.t_wakeup_ns = (u16)temp; OF_DC_LOG("phy t_wakeup_ns %d\n", dsi->phy_timing.t_wakeup_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-taget", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-taget", &temp)) { dsi->phy_timing.t_taget_ns = (u16)temp; OF_DC_LOG("phy t_taget_ns %d\n", dsi->phy_timing.t_taget_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-tasure", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-tasure", &temp)) { dsi->phy_timing.t_tasure_ns = (u16)temp; OF_DC_LOG("phy t_tasure_ns %d\n", dsi->phy_timing.t_tasure_ns); } - if (!of_property_read_u32(np_panel, "nvidia,dsi-phy-tago", &temp)) { + if (!of_property_read_u32(np_dsi_panel, + "nvidia,dsi-phy-tago", &temp)) { dsi->phy_timing.t_tago_ns = (u16)temp; OF_DC_LOG("phy t_tago_ns %d\n", dsi->phy_timing.t_tago_ns); } - if (!of_find_property(np_panel, "nvidia,dsi-boardinfo", NULL)) { - of_property_read_u32_index(np_panel, + if (!of_find_property(np_dsi_panel, + "nvidia,dsi-boardinfo", NULL)) { + of_property_read_u32_index(np_dsi_panel, "nvidia,dsi-boardinfo", 0, &dsi->boardinfo.platform_boardid); - of_property_read_u32_index(np_panel, + of_property_read_u32_index(np_dsi_panel, "nvidia,dsi-boardinfo", 1, &dsi->boardinfo.platform_boardversion); - of_property_read_u32_index(np_panel, + of_property_read_u32_index(np_dsi_panel, "nvidia,dsi-boardinfo", 2, &dsi->boardinfo.display_boardid); - of_property_read_u32_index(np_panel, + of_property_read_u32_index(np_dsi_panel, "nvidia,dsi-boardinfo", 3, &dsi->boardinfo.display_boardversion); @@ -1345,7 +1294,7 @@ int parse_dsi_settings(struct platform_device *ndev, dsi->boardinfo.display_boardversion); } - return 0; + return np_dsi_panel; } static int dc_hdmi_out_enable(struct device *dev) @@ -1473,8 +1422,9 @@ struct tegra_dc_platform_data struct tegra_dc_platform_data *pdata; struct device_node *np = ndev->dev.of_node; struct device_node *np_dsi = NULL; + struct device_node *np_dsi_panel = NULL; struct device_node *timings_np = NULL; - struct device_node *fb_np = NULL; + struct device_node *np_target_disp = NULL; struct device_node *sd_np = NULL; struct device_node *default_out_np = NULL; struct device_node *entry = NULL; @@ -1512,28 +1462,113 @@ struct tegra_dc_platform_data } /* - * determine dc out type + * determine dc out type, + * dc node defines nvidia,out-type to indicate + * what out type of display is used for + * current dc id. */ - default_out_np = of_find_node_by_name(np, "dc-default-out"); + + err = parse_dc_out_type(np, pdata->default_out); + if (err) { + pr_err("parse_dc_out_type err\n"); + goto fail_parse; + } + + if (!of_property_read_u32(np, "nvidia,out-rotation", &temp)) { + pdata->default_out->rotation = (unsigned) temp; + OF_DC_LOG("out_rotation %d\n", temp); + } + + if (!of_property_read_u32(np, "nvidia,fb-bpp", &temp)) { + pdata->fb->bits_per_pixel = (int)temp; + OF_DC_LOG("fb bpp %d\n", pdata->fb->bits_per_pixel); + } else { + goto fail_parse; + } + + if (!of_property_read_u32(np, "nvidia,fb-flags", &temp)) { + if (temp == TEGRA_FB_FLIP_ON_PROBE) + OF_DC_LOG("fb flip on probe\n"); + else if (temp == 0) + OF_DC_LOG("do not flip fb on probe time\n"); + else { + pr_err("invalid fb_flags\n"); + goto fail_parse; + } + pdata->fb->flags = (unsigned long)temp; + } + + if (pdata->default_out->type == TEGRA_DC_OUT_DSI) { + np_dsi = of_find_node_by_path(DSI_NODE); + + if (!np_dsi) { + pr_err("%s: could not find dsi node\n", __func__); + goto fail_parse; + } else if (of_device_is_available(np_dsi)) { + pdata->default_out->dsi = devm_kzalloc(&ndev->dev, + sizeof(struct tegra_dsi_out), GFP_KERNEL); + if (!pdata->default_out->dsi) { + dev_err(&ndev->dev, "not enough memory\n"); + goto fail_parse; + } + np_dsi_panel = parse_dsi_settings(ndev, np_dsi, + pdata); + if (!np_dsi_panel) + goto fail_parse; + else + np_target_disp = np_dsi_panel; + } + } else if (pdata->default_out->type == TEGRA_DC_OUT_HDMI) { + bool hotplug_report = false; + struct device_node *np_hdmi = + of_find_node_by_path(HDMI_NODE); + + if (np_hdmi && of_device_is_available(np_hdmi)) { + if (!of_property_read_u32(np_hdmi, + "nvidia,hotplug-report", &temp)) { + hotplug_report = (bool)temp; + } + } + + pdata->default_out->enable = dc_hdmi_out_enable; + pdata->default_out->disable = dc_hdmi_out_disable; + pdata->default_out->hotplug_init = dc_hdmi_hotplug_init; + pdata->default_out->postsuspend = dc_hdmi_postsuspend; +#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \ + defined(CONFIG_ARCH_TEGRA_12x_SOC) + if (hotplug_report) + pdata->default_out->hotplug_report = + dc_hdmi_hotplug_report; +#endif + np_target_disp = + of_get_child_by_name(np_hdmi, "hdmi-display"); + if (!np_target_disp || + !of_device_is_available(np_target_disp)) { + pr_err("/hdmi/hdmi-display node is NOT valid\n"); + goto fail_parse; + } + } + + default_out_np = of_get_child_by_name(np_target_disp, + "disp-default-out"); if (!default_out_np) { - pr_err("%s: could not find dc-default-out node\n", + pr_err("%s: could not find disp-default-out node\n", __func__); goto fail_parse; } else { - err = parse_dc_default_out(ndev, default_out_np, - pdata->default_out); + err = parse_disp_default_out(ndev, default_out_np, + pdata->default_out, pdata->fb); if (err) goto fail_parse; } -#ifndef CONFIG_TEGRA_HDMI_PRIMARY - if (pdata->default_out->type == TEGRA_DC_OUT_DSI) - timings_np = of_find_node_by_path(DC0_DISP_TIMINGS); - else - timings_np = of_find_node_by_path(DC1_DISP_TIMINGS); -#else - timings_np = of_find_node_by_path(DC0_DISP_TIMINGS); -#endif + err = parse_tmds_config(ndev, np_target_disp, + pdata->default_out); + if (err) + goto fail_parse; + + timings_np = of_get_child_by_name(np_target_disp, + "display-timings"); if (!timings_np) { if (pdata->default_out->type == TEGRA_DC_OUT_DSI) { pr_err("%s: could not find display-timings node\n", @@ -1581,14 +1616,9 @@ struct tegra_dc_platform_data } #endif } -#ifndef CONFIG_TEGRA_HDMI_PRIMARY - if (pdata->default_out->type == TEGRA_DC_OUT_DSI) - sd_np = of_find_node_by_path(DC0_SMARTDIMMER); - else - sd_np = of_find_node_by_path(DC1_SMARTDIMMER); -#else - sd_np = of_find_node_by_path(DC0_SMARTDIMMER); -#endif + + sd_np = of_get_child_by_name(np_target_disp, + "smartdimmer"); if (!sd_np) { pr_info("%s: could not find SD settings node\n", __func__); @@ -1609,14 +1639,9 @@ struct tegra_dc_platform_data } #ifdef CONFIG_TEGRA_DC_CMU -#ifndef CONFIG_TEGRA_HDMI_PRIMARY - if (pdata->default_out->type == TEGRA_DC_OUT_DSI) - cmu_np = of_find_node_by_path(DC0_CMU); - else - cmu_np = of_find_node_by_path(DC1_CMU); -#else - cmu_np = of_find_node_by_path(DC0_CMU); -#endif + cmu_np = of_get_child_by_name(np_target_disp, + "cmu"); + if (!cmu_np) { pr_info("%s: could not find cmu node\n", __func__); @@ -1635,44 +1660,6 @@ struct tegra_dc_platform_data } #endif - if (pdata->default_out->type == TEGRA_DC_OUT_DSI) { - np_dsi = of_find_node_by_path(DSI_NODE); - - if (!np_dsi) { - pr_err("%s: could not find dsi node\n", __func__); - goto fail_parse; - } else if (of_device_is_available(np_dsi)) { - pdata->default_out->dsi = devm_kzalloc(&ndev->dev, - sizeof(struct tegra_dsi_out), GFP_KERNEL); - if (!pdata->default_out->dsi) { - dev_err(&ndev->dev, "not enough memory\n"); - goto fail_parse; - } - } - } else if (pdata->default_out->type == TEGRA_DC_OUT_HDMI) { - bool hotplug_report = false; - struct device_node *np_hdmi = - of_find_node_by_path(HDMI_NODE); - - if (np_hdmi && of_device_is_available(np_hdmi)) { - if (!of_property_read_u32(np_hdmi, - "nvidia,hotplug-report", &temp)) { - hotplug_report = (bool)temp; - } - } - - pdata->default_out->enable = dc_hdmi_out_enable; - pdata->default_out->disable = dc_hdmi_out_disable; - pdata->default_out->hotplug_init = dc_hdmi_hotplug_init; - pdata->default_out->postsuspend = dc_hdmi_postsuspend; -#if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) - if (hotplug_report) - pdata->default_out->hotplug_report = - dc_hdmi_hotplug_report; -#endif - } - /* * parse sd_settings values */ @@ -1701,31 +1688,6 @@ struct tegra_dc_platform_data } #endif - if (pdata->default_out->dsi) { - /* It happens in case of TEGRA_DC_OUT_DSI only */ - err = parse_dsi_settings(ndev, np_dsi, pdata); - if (err) - goto fail_parse; - } - -#ifndef CONFIG_TEGRA_HDMI_PRIMARY - if (pdata->default_out->type == TEGRA_DC_OUT_DSI) - fb_np = of_find_node_by_path(DC0_FRAMEBUFFER_DATA); - else - fb_np = of_find_node_by_path(DC1_FRAMEBUFFER_DATA); -#else - fb_np = of_find_node_by_path(DC0_FRAMEBUFFER_DATA); -#endif - if (!fb_np) { - pr_err("%s: err, No framebuffer-data\n", - __func__); - goto fail_parse; - } else { - err = parse_fb_info(fb_np, pdata->fb); - if (err) - goto fail_parse; - } - if (!of_property_read_u32(np, "nvidia,dc-flags", &temp)) { if ((temp != TEGRA_DC_FLAG_ENABLED) && (temp != 0)) { diff --git a/include/dt-bindings/display/tegra-panel.h b/include/dt-bindings/display/tegra-panel.h index 16c8b357649a..67d5fe5c1096 100644 --- a/include/dt-bindings/display/tegra-panel.h +++ b/include/dt-bindings/display/tegra-panel.h @@ -1,7 +1,7 @@ /* * include/dt-bindings/display/tegra-panel.h * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -114,4 +114,10 @@ #define DSI_INSTANCE_0 0 #define DSI_INSTANCE_1 1 +/* Aggressiveness level of DSI suspend. The higher, the more aggressive. */ +#define DSI_NO_SUSPEND 0 +#define DSI_HOST_SUSPEND_LV0 1 +#define DSI_HOST_SUSPEND_LV1 2 +#define DSI_HOST_SUSPEND_LV2 3 + #endif /* __TEGRA_PANEL_H */ |