diff options
| -rwxr-xr-x | arch/arm/mach-tegra/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 110 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/common.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/cpuidle-t11x.c | 10 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/cpuidle-t14x.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/devices.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 41 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 67 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/reset.c | 59 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t20.S | 9 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 10 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 20 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep.h | 12 | ||||
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 9 | ||||
| -rw-r--r-- | drivers/clocksource/tegra-tsc-timer.c | 9 | ||||
| -rw-r--r-- | drivers/watchdog/tegra_wdt.c | 191 | ||||
| -rw-r--r-- | include/linux/tegra-soc.h | 3 | ||||
| -rw-r--r-- | security/tf_driver/Kconfig | 1 | ||||
| -rw-r--r-- | security/tlk_driver/Kconfig | 1 |
21 files changed, 312 insertions, 272 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index bb65df4d5b27..9167cf8f43f7 100755 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -912,14 +912,6 @@ config TEGRA_SOCTHERM help Enables use of soctherm for thermal management. -config TEGRA_USE_SECURE_KERNEL - bool "Boot the linux kernel in non-secure mode" - help - When enabled, the CPU will boot in the non-secure mode and issue - SMCs in order to access secure registers. SMC requests would be - serviced by a third party software component running in the secure - mode. - config TEGRA_VIRTUAL_CPUID bool "virtualized CPUID" depends on !TEGRA_USE_SECURE_KERNEL diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index f9362bcbbbf3..27b7754bfb71 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -169,7 +169,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o obj-y += board-common.o obj-$(CONFIG_TEGRA_WAKEUP_MONITOR) += tegra_wakeup_monitor.o -obj-$(CONFIG_TEGRA_USE_SECURE_KERNEL) += tegra_tzram.o +obj-$(CONFIG_TRUSTED_LITTLE_KERNEL) += tegra_tzram.o obj-${CONFIG_MACH_BONAIRE} += board-bonaire.o obj-${CONFIG_MACH_BONAIRE} += board-bonaire-panel.o diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index b17e3f0fa752..5d3912b226a2 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -139,7 +139,7 @@ phys_addr_t tegra_wb0_params_block_size; #ifdef CONFIG_TEGRA_NVDUMPER unsigned long nvdumper_reserved; #endif -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL +#ifdef CONFIG_TRUSTED_LITTLE_KERNEL unsigned long tegra_tzram_start; unsigned long tegra_tzram_size; #endif @@ -571,7 +571,6 @@ static __initdata struct tegra_clk_init_table tegra14x_cbus_init_table[] = { #endif #ifdef CONFIG_CACHE_L2X0 -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL static void tegra_cache_smc(bool enable, u32 arg) { void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE); @@ -640,76 +639,73 @@ static void tegra_l2x0_disable(void) tegra_cache_smc(false, l2x0_way_mask); local_irq_restore(flags); } -#endif /* CONFIG_TEGRA_USE_SECURE_KERNEL */ void tegra_init_cache(bool init) { void __iomem *p = IO_ADDRESS(TEGRA_ARM_PL310_BASE); u32 aux_ctrl; -#ifndef CONFIG_TEGRA_USE_SECURE_KERNEL u32 cache_type; u32 tag_latency, data_latency; -#endif -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL - /* issue the SMC to enable the L2 */ - aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); - trace_smc_init_cache(NVSEC_SMC_START); - tegra_cache_smc(true, aux_ctrl); - trace_smc_init_cache(NVSEC_SMC_DONE); + if (!is_secure_mode()) { + /* issue the SMC to enable the L2 */ + aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); + trace_smc_init_cache(NVSEC_SMC_START); + tegra_cache_smc(true, aux_ctrl); + trace_smc_init_cache(NVSEC_SMC_DONE); - /* after init, reread aux_ctrl and register handlers */ - aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); - l2x0_init(p, aux_ctrl, 0xFFFFFFFF); + /* after init, reread aux_ctrl and register handlers */ + aux_ctrl = readl_relaxed(p + L2X0_AUX_CTRL); + l2x0_init(p, aux_ctrl, 0xFFFFFFFF); - /* override outer_disable() with our disable */ - outer_cache.disable = tegra_l2x0_disable; -#else + /* override outer_disable() with our disable */ + outer_cache.disable = tegra_l2x0_disable; + } else { #if defined(CONFIG_ARCH_TEGRA_2x_SOC) - tag_latency = 0x331; - data_latency = 0x441; + tag_latency = 0x331; + data_latency = 0x441; #else - if (!tegra_platform_is_silicon()) { - tag_latency = 0x770; - data_latency = 0x770; - } else if (is_lp_cluster()) { - tag_latency = tegra_cpu_c1_l2_tag_latency; - data_latency = tegra_cpu_c1_l2_data_latency; - } else { - tag_latency = tegra_cpu_c0_l2_tag_latency; - data_latency = tegra_cpu_c0_l2_data_latency; - } + if (!tegra_platform_is_silicon()) { + tag_latency = 0x770; + data_latency = 0x770; + } else if (is_lp_cluster()) { + tag_latency = tegra_cpu_c1_l2_tag_latency; + data_latency = tegra_cpu_c1_l2_data_latency; + } else { + tag_latency = tegra_cpu_c0_l2_tag_latency; + data_latency = tegra_cpu_c0_l2_data_latency; + } #endif - writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); + writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL); #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) - if (!tegra_platform_is_fpga()) { + if (!tegra_platform_is_fpga()) { #ifdef CONFIG_ARCH_TEGRA_14x_SOC - /* Enable double line fill */ - writel(0x40000007, p + L2X0_PREFETCH_CTRL); + /* Enable double line fill */ + writel(0x40000007, p + L2X0_PREFETCH_CTRL); #else - writel(0x7, p + L2X0_PREFETCH_CTRL); + writel(0x7, p + L2X0_PREFETCH_CTRL); #endif - writel(0x3, p + L2X0_POWER_CTRL); - } + writel(0x3, p + L2X0_POWER_CTRL); + } #endif - cache_type = readl(p + L2X0_CACHE_TYPE); - aux_ctrl = (cache_type & 0x700) << (17-8); - aux_ctrl |= 0x7C400001; - if (init) { - l2x0_init(p, aux_ctrl, 0x8200c3fe); - } else { - u32 tmp; + cache_type = readl(p + L2X0_CACHE_TYPE); + aux_ctrl = (cache_type & 0x700) << (17-8); + aux_ctrl |= 0x7C400001; + if (init) { + l2x0_init(p, aux_ctrl, 0x8200c3fe); + } else { + u32 tmp; - tmp = aux_ctrl; - aux_ctrl = readl(p + L2X0_AUX_CTRL); - aux_ctrl &= 0x8200c3fe; - aux_ctrl |= tmp; - writel(aux_ctrl, p + L2X0_AUX_CTRL); + tmp = aux_ctrl; + aux_ctrl = readl(p + L2X0_AUX_CTRL); + aux_ctrl &= 0x8200c3fe; + aux_ctrl |= tmp; + writel(aux_ctrl, p + L2X0_AUX_CTRL); + } + l2x0_enable(); } - l2x0_enable(); -#endif } #endif @@ -1150,7 +1146,7 @@ static int __init tegra_tsec_arg(char *options) } early_param("tsec", tegra_tsec_arg); -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL +#ifdef CONFIG_TRUSTED_LITTLE_KERNEL static int __init tegra_tzram_arg(char *options) { char *p = options; @@ -2088,11 +2084,11 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size, } #endif -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL - pr_info("Tzram: %08lx - %08lx\n", - tegra_tzram_start, - tegra_tzram_size ? - tegra_tzram_start + tegra_tzram_size - 1 : 0); +#ifdef CONFIG_TRUSTED_LITTLE_KERNEL + pr_info("Tzram: %08lx - %08lx\n", + tegra_tzram_start, + tegra_tzram_size ? + tegra_tzram_start + tegra_tzram_size - 1 : 0); #endif #ifdef CONFIG_TEGRA_USE_NCT diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 49356b0a8709..1d178340430f 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -1,4 +1,6 @@ /* + * Copyright (C) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -20,7 +22,7 @@ extern struct smp_operations tegra_smp_ops; extern phys_addr_t tegra_tsec_start; extern phys_addr_t tegra_tsec_size; -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL +#ifdef CONFIG_TRUSTED_LITTLE_KERNEL extern unsigned long tegra_tzram_start; extern unsigned long tegra_tzram_size; #endif diff --git a/arch/arm/mach-tegra/cpuidle-t11x.c b/arch/arm/mach-tegra/cpuidle-t11x.c index 360635909dea..f0166c9ac95b 100644 --- a/arch/arm/mach-tegra/cpuidle-t11x.c +++ b/arch/arm/mach-tegra/cpuidle-t11x.c @@ -456,13 +456,13 @@ static bool tegra_cpu_core_power_down(struct cpuidle_device *dev, tegra_cpu_wake_by_time[dev->cpu] = ktime_to_us(entry_time) + request; smp_wmb(); -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL - if ((cpu == 0) || (cpu == 4)) { - tegra_generic_smc(0x84000001, ((1 << 16) | 5), + if (!is_secure_mode()) + if ((cpu == 0) || (cpu == 4)) { + tegra_generic_smc(0x84000001, ((1 << 16) | 5), (TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset)); - } -#endif + } + cpu_suspend(0, tegra3_sleep_cpu_secondary_finish); tegra11x_restore_vmin(); diff --git a/arch/arm/mach-tegra/cpuidle-t14x.c b/arch/arm/mach-tegra/cpuidle-t14x.c index 3af1eece7441..ae560f572265 100644 --- a/arch/arm/mach-tegra/cpuidle-t14x.c +++ b/arch/arm/mach-tegra/cpuidle-t14x.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/cpuidle-t14x.c * - * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved. + * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -449,13 +449,12 @@ static bool tegra_cpu_core_power_down(struct cpuidle_device *dev, tegra_cpu_wake_by_time[dev->cpu] = ktime_to_us(entry_time) + request; smp_wmb(); -#ifdef CONFIG_TRUSTED_LITTLE_KERNEL - if (dev->cpu == 0) { - tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4, + if (!is_secure_mode()) + if (dev->cpu == 0) { + tegra_generic_smc(0xFFFFFFFC, 0xFFFFFFE4, (TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset)); - } -#endif + } cpu_suspend(0, tegra3_sleep_cpu_secondary_finish); tegra_cpu_wake_by_time[dev->cpu] = LLONG_MAX; diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index c0b3485b6233..182831fafa31 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -2497,8 +2497,7 @@ static struct resource tegra_wdt0_resources[] = { .flags = IORESOURCE_MEM, }, #endif -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) [5] = { .start = TEGRA_WDT4_BASE, .end = TEGRA_WDT4_BASE + TEGRA_WDT4_SIZE - 1, diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 6103578ace41..0c55f4d5d81e 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -3,7 +3,7 @@ * * CPU initialization routines for Tegra SoCs * - * Copyright (c) 2009-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2009-2014, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011 Google, Inc. * Author: Colin Cross <ccross@android.com> * Gary King <gking@nvidia.com> @@ -39,6 +39,15 @@ #define RESET_DATA_PHYS (TEGRA_RESET_HANDLER_BASE \ + __tegra_cpu_reset_handler_data - __tegra_cpu_reset_handler_start) + +ENTRY(is_secure_mode) + mrc p14, 0, r0, c0, c1, 0 @ dbgdscr + tst r0, #(1 << 18) @ dbgdscr.ns + moveq r0, #1 + movne r0, #0 + mov pc, lr @ return + + #ifdef CONFIG_SMP /* * tegra_secondary_startup @@ -50,8 +59,10 @@ __CPUINIT ENTRY(tegra_secondary_startup) bl __invalidate_cpu_state + bl is_secure_mode + cmp r0, #1 + bne secondary_startup @ non-secure skip -#ifndef CONFIG_TEGRA_USE_SECURE_KERNEL /* enable user space perf counter access */ /* only accessible in secure state */ mrc p15, 0, r0, c9, c12, 0 @@ -64,7 +75,6 @@ ENTRY(tegra_secondary_startup) mcr p15, 0, r1, c9, c14, 2 mov r0, #1 mcr p15, 0, r0, c9, c14, 0 -#endif b secondary_startup ENDPROC(tegra_secondary_startup) @@ -80,13 +90,14 @@ ENDPROC(tegra_secondary_startup) * re-enabling sdram. */ ENTRY(tegra_resume) -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL + bl is_secure_mode + cmp r0, #1 + beq 1f @ secure-mode skip mov32 r1, TEGRA_TMRUS_BASE ldr r0, [r1] adr r1, tegra_resume_entry_time str r0, [r1] -#endif - +1: bl __invalidate_cpu_state cpu_id r0 @@ -136,8 +147,10 @@ ENTRY(tegra_resume) #endif /* CONFIG_TRUSTED_FOUNDATIONS */ #ifdef CONFIG_CACHE_L2X0 -#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - !defined(CONFIG_ARCH_TEGRA_14x_SOC) +#if !defined(CONFIG_ARCH_TEGRA_14x_SOC) + bl is_secure_mode + cmp r0, #1 + bne no_l2_init @ secure-mode skip adr r0, tegra_resume_l2_init ldr r1, [r0] tst r1, #1 @@ -189,13 +202,12 @@ ENTRY(tegra_resume) str r2, [r3, #L2X0_AUX_CTRL] mov r2, #1 str r2, [r3, #L2X0_CTRL] -#endif /* ?CONFIG_TEGRA_USE_SECURE_KERNEL */ +#endif #endif /* CONFIG_CACHE_L2X0 */ no_l2_init: b cpu_resume ENDPROC(tegra_resume) -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL .globl tegra_resume_timestamps_start #ifndef CONFIG_ARCH_TEGRA_11x_SOC .globl tegra_resume_smc_entry_time @@ -213,7 +225,6 @@ tegra_resume_smc_exit_time: tegra_resume_entry_time: .long 0 tegra_resume_timestamps_end: -#endif /* CONFIG_TEGRA_USE_SECURE_KERNEL */ #ifdef CONFIG_CACHE_L2X0 .globl tegra_resume_l2_init tegra_resume_l2_init: @@ -244,8 +255,11 @@ __invalidate_cpu_state: ldr r0, =0x410fc09 teq r1, r0 beq cortex_a9 - -#ifndef CONFIG_TEGRA_USE_SECURE_KERNEL + mov r1, lr @ save LR + bl is_secure_mode + cmp r0, #1 + mov lr, r1 @ restore LR + bne __enable_i_cache_branch_pred @ if not in secure mode skip mrc p15, 0x1, r0, c15, c0, 3 @ L2 prefetch control reg tst r0, #0x1000 orreq r0, r0, #0x1000 @ disable throttling @@ -273,7 +287,6 @@ __invalidate_cpu_state: mrc p15, 0x1, r0, c15, c0, 0 @ L2 ACTLR orr r0, r0, #0x80 @ hazard detection timeout mcr p15, 0x1, r0, c15, c0, 0 -#endif __enable_i_cache_branch_pred: mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x1800 diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index dad0710fdf41..31a39c833f8c 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -702,25 +702,26 @@ bool tegra_set_cpu_in_pd(int cpu) static void tegra_sleep_core(enum tegra_suspend_mode mode, unsigned long v2p) { -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL - outer_flush_range(__pa(&tegra_resume_timestamps_start), + if (!is_secure_mode()) { + outer_flush_range(__pa(&tegra_resume_timestamps_start), __pa(&tegra_resume_timestamps_end)); - if (mode == TEGRA_SUSPEND_LP0) { - trace_smc_sleep_core(NVSEC_SMC_START); + if (mode == TEGRA_SUSPEND_LP0) { + trace_smc_sleep_core(NVSEC_SMC_START); tegra_generic_smc(0x84000001, ((1 << 16) | (1 << 24) | 1), virt_to_phys(tegra_resume)); - } else { - trace_smc_sleep_core(NVSEC_SMC_START); + } else { + trace_smc_sleep_core(NVSEC_SMC_START); tegra_generic_smc(0x84000001, ((1 << 16) | 2), (TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset)); + } + + trace_smc_sleep_core(NVSEC_SMC_DONE); } - trace_smc_sleep_core(NVSEC_SMC_DONE); -#endif tegra_get_suspend_time(); #ifdef CONFIG_ARCH_TEGRA_2x_SOC cpu_suspend(v2p, tegra2_sleep_core_finish); @@ -736,17 +737,17 @@ static inline void tegra_sleep_cpu(unsigned long v2p) static inline void tegra_stop_mc_clk(unsigned long v2p) { -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL - outer_flush_range(__pa(&tegra_resume_timestamps_start), + if (!is_secure_mode()) { + outer_flush_range(__pa(&tegra_resume_timestamps_start), __pa(&tegra_resume_timestamps_end)); - trace_smc_sleep_core(NVSEC_SMC_START); + trace_smc_sleep_core(NVSEC_SMC_START); tegra_generic_smc(0x84000001, ((1 << 16) | 3), (TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset)); - trace_smc_sleep_core(NVSEC_SMC_DONE); -#endif + trace_smc_sleep_core(NVSEC_SMC_DONE); + } cpu_suspend(v2p, tegra3_stop_mc_clk_finish); } @@ -832,14 +833,18 @@ unsigned int tegra_idle_power_down_last(unsigned int sleep_time, suspend_cpu_complex(flags); tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog); #if defined(CONFIG_CACHE_L2X0) -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) - flush_cache_all(); - outer_disable(); -#elif !defined(CONFIG_ARCH_TEGRA_14x_SOC) - tegra_resume_l2_init = 1; - __cpuc_flush_dcache_area(&tegra_resume_l2_init, sizeof(unsigned long)); - outer_flush_range(__pa(&tegra_resume_l2_init), + if (!is_secure_mode()) { + flush_cache_all(); + outer_disable(); + } +#if !defined(CONFIG_ARCH_TEGRA_14x_SOC) + else { + tegra_resume_l2_init = 1; + __cpuc_flush_dcache_area(&tegra_resume_l2_init, + sizeof(unsigned long)); + outer_flush_range(__pa(&tegra_resume_l2_init), __pa(&tegra_resume_l2_init) + sizeof(unsigned long)); + } #endif #endif @@ -887,8 +892,9 @@ unsigned int tegra_idle_power_down_last(unsigned int sleep_time, #if defined(CONFIG_ARCH_TEGRA_14x_SOC) tegra_init_cache(true); -#elif defined(CONFIG_TEGRA_USE_SECURE_KERNEL) - tegra_init_cache(false); +#else + if (!is_secure_mode()) + tegra_init_cache(false); #endif #if defined(CONFIG_TRUSTED_FOUNDATIONS) @@ -1433,17 +1439,17 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags) } #endif -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) + if (!is_secure_mode()) { #ifndef CONFIG_ARCH_TEGRA_11x_SOC - trace_smc_wake(tegra_resume_smc_entry_time, NVSEC_SMC_START); - trace_smc_wake(tegra_resume_smc_exit_time, NVSEC_SMC_DONE); + trace_smc_wake(tegra_resume_smc_entry_time, NVSEC_SMC_START); + trace_smc_wake(tegra_resume_smc_exit_time, NVSEC_SMC_DONE); #endif - if (mode == TEGRA_SUSPEND_LP0) { - trace_secureos_init(tegra_resume_entry_time, + if (mode == TEGRA_SUSPEND_LP0) { + trace_secureos_init(tegra_resume_entry_time, NVSEC_SUSPEND_EXIT_DONE); + } } -#endif if (mode == TEGRA_SUSPEND_LP0) { @@ -2241,8 +2247,7 @@ late_initcall(tegra_pm_core_debug_init); #ifdef CONFIG_DEBUG_RODATA void set_platform_text_rw(void) { -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL - set_memory_rw((unsigned long)tegra_generic_smc, 1); -#endif + if (!is_secure_mode()) + set_memory_rw((unsigned long)tegra_generic_smc, 1); } #endif diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 258847e3490c..b2981e2ab962 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -6,7 +6,7 @@ * Author: * Colin Cross <ccross@google.com> * - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -341,9 +341,7 @@ void tegra_smp_save_power_mask(void); void tegra_smp_restore_power_mask(void); #endif -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL void tegra_generic_smc(u32 type, u32 subtype, u32 arg); -#endif /* The debug channel uart base physical address */ extern unsigned long debug_uart_port_base; diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index d0743e6b7e48..683c2d9a48ea 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/reset.c * - * Copyright (C) 2011-2013, NVIDIA Corporation. All rights reserved. + * Copyright (C) 2011-2014, NVIDIA Corporation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -38,40 +38,47 @@ static bool is_enabled; static void tegra_cpu_reset_handler_enable(void) { void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_BASE); -#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) - void __iomem *evp_cpu_reset = - IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); - void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); + void __iomem *evp_cpu_reset; + void __iomem *sb_ctrl; unsigned long reg; -#endif + + if (is_secure_mode()) { + evp_cpu_reset = + IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); + sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); + } + BUG_ON(is_enabled); BUG_ON(tegra_cpu_reset_handler_size > TEGRA_RESET_HANDLER_SIZE); memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, tegra_cpu_reset_handler_size); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) - tegra_generic_smc(0x82000001, - TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset, 0); -#else - /* NOTE: This must be the one and only write to the EVP CPU reset - vector in the entire system. */ - writel(TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset, - evp_cpu_reset); - wmb(); - reg = readl(evp_cpu_reset); - - /* - * Prevent further modifications to the physical reset vector. - * NOTE: Has no effect on chips prior to Tegra30. - */ - if (tegra_get_chip_id() != TEGRA_CHIPID_TEGRA2) { - reg = readl(sb_ctrl); - reg |= 2; - writel(reg, sb_ctrl); + if (!is_secure_mode()) { + tegra_generic_smc(0x82000001, + TEGRA_RESET_HANDLER_BASE + + tegra_cpu_reset_handler_offset, 0); + } else { + + /* NOTE: This must be the one and only write to the EVP + * CPU reset vector in the entire system. + */ + writel(TEGRA_RESET_HANDLER_BASE + + tegra_cpu_reset_handler_offset, evp_cpu_reset); wmb(); + reg = readl(evp_cpu_reset); + + /* + * Prevent further modifications to the physical reset vector. + * NOTE: Has no effect on chips prior to Tegra30. + */ + if (tegra_get_chip_id() != TEGRA_CHIPID_TEGRA2) { + reg = readl(sb_ctrl); + reg |= 2; + writel(reg, sb_ctrl); + wmb(); + } } -#endif is_enabled = true; } diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S index 194f5363a076..1e4ce255046e 100644 --- a/arch/arm/mach-tegra/sleep-t20.S +++ b/arch/arm/mach-tegra/sleep-t20.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA Corporation. All rights reserved. * Copyright (c) 2011, Google, Inc. * * Author: Colin Cross <ccross@android.com> @@ -277,7 +277,10 @@ ENTRY(tegra2_lp1_reset) * enable PLLP. */ mov32 r0, TEGRA_CLK_RESET_BASE -#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) + bl is_secure_mode + cmp r0, #1 + mov32 r0, TEGRA_CLK_RESET_BASE + bne 1f @Skip if non-secure mode /* secure code handles 32KHz to CLKM/OSC clock switch */ mov r1, #(1 << 28) str r1, [r0, #CLK_RESET_SCLK_BURST] @@ -285,7 +288,7 @@ ENTRY(tegra2_lp1_reset) mov r1, #0 str r1, [r0, #CLK_RESET_SCLK_DIVIDER] str r1, [r0, #CLK_RESET_CCLK_DIVIDER] -#endif +1: ldr r1, [r0, #CLK_RESET_PLLM_BASE] tst r1, #(1 << 30) orreq r1, r1, #(1 << 30) diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 98e836ca8f3a..e64cad95d2f3 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -456,7 +456,10 @@ enable_mc: resume_lp1: mov32 r0, TEGRA_CLK_RESET_BASE -#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) + bl is_secure_mode + cmp r0, #1 + mov32 r0, TEGRA_CLK_RESET_BASE + bne 1f @Skip if non-secure mode /* secure code handles 32KHz to CLKM/OSC clock switch */ mov r1, #(1<<28) str r1, [r0, #CLK_RESET_SCLK_BURST] @@ -464,8 +467,7 @@ resume_lp1: mov r1, #0 str r1, [r0, #CLK_RESET_SCLK_DIVIDER] str r1, [r0, #CLK_RESET_CCLK_DIVIDER] -#endif - +1: #if defined(CONFIG_ARCH_TEGRA_3x_SOC) /* enable PLLM via PMC */ mov32 r2, TEGRA_PMC_BASE diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 75ed8db27990..099de4590c23 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -208,15 +208,15 @@ ENDPROC(tegra_flush_l1_cache) */ ENTRY(tegra_sleep_cpu_finish) mov r4, r0 -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) + bl is_secure_mode + cmp r0, #1 + beq 1f @if in secure-mode skip ldr r0, =0x84000001 ldr r1, =((1 << 16) | 4) ldr r2, =TEGRA_RESET_HANDLER_BASE bl tegra_generic_smc -#endif - +1: bl tegra_flush_cache - mov r0, r4 bl tegra_cpu_exit_coherency @@ -298,8 +298,12 @@ tegra_shut_off_mmu: dsb mcr p15, 0, r3, c1, c0, 0 isb -#if defined(CONFIG_CACHE_L2X0) && \ - !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) +#if defined(CONFIG_CACHE_L2X0) + mov r5, r0 @save r0 + bl is_secure_mode + cmp r0, #1 + mov r0, r5 @restore r0 + bne 2f @if non-secure mode skip tst r11, #1 beq 2f mov32 r1, TEGRA_ARM_PL310_BASE @@ -318,7 +322,7 @@ tegra_shut_off_mmu: mov r2, #0 str r2, [r1, #L2X0_CACHE_SYNC] str r2, [r1, #L2X0_CTRL] -#endif /* CONFIG_CACHE_L2X0 && !CONFIG_TEGRA_USE_SECURE_KERNEL */ +#endif /* CONFIG_CACHE_L2X0 */ 2: mov pc, r0 /* @@ -338,7 +342,6 @@ ENTRY(tegra_cpu_pllp) ENDPROC(tegra_cpu_pllp) #endif -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) /* * tegra_generic_smc * @@ -364,4 +367,3 @@ restart: done: mov pc, lr ENDPROC(tegra_generic_smc) -#endif diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 0140b0ea6f6c..607b78fb3032 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,14 +19,6 @@ #include "iomap.h" -#ifndef CONFIG_TEGRA_USE_SECURE_KERNEL -/* FIXME: The code associated with this should be removed if our change to - save the diagnostic regsiter in the CPU context is accepted. */ -#define USE_TEGRA_DIAG_REG_SAVE 1 -#else -#define USE_TEGRA_DIAG_REG_SAVE 0 -#endif - #define TEGRA_POWER_LP1_AUDIO (1 << 25) /* do not turn off pll-p in LP1 */ #ifdef CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE @@ -346,7 +338,6 @@ int tegra3_sleep_cpu_secondary_finish(unsigned long int); int tegra3_stop_mc_clk_finish(unsigned long int); #endif -#ifdef CONFIG_TEGRA_USE_SECURE_KERNEL extern unsigned long tegra_resume_timestamps_start; extern unsigned long tegra_resume_timestamps_end; #ifndef CONFIG_ARCH_TEGRA_11x_SOC @@ -354,7 +345,6 @@ extern unsigned long tegra_resume_smc_entry_time; extern unsigned long tegra_resume_smc_exit_time; #endif extern unsigned long tegra_resume_entry_time; -#endif #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_PM_SLEEP) extern unsigned long tegra_resume_l2_init; #endif diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 161004180cf5..d6c71f901575 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1,5 +1,6 @@ /* * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support + * Copyright (c) 2007-2014, NVIDIA CORPORATION. All rights reserved. * * Copyright (C) 2007 ARM Limited * @@ -97,12 +98,12 @@ static inline void l2x0_inv_line(unsigned long addr) writel_relaxed(addr, base + L2X0_INV_LINE_PA); } -#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - (defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)) +#if (defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)) static inline void debug_writel(unsigned long val) { - if (outer_cache.set_debug) - outer_cache.set_debug(val); + if (is_secure_mode()) + if (outer_cache.set_debug) + outer_cache.set_debug(val); } static void pl310_set_debug(unsigned long val) diff --git a/drivers/clocksource/tegra-tsc-timer.c b/drivers/clocksource/tegra-tsc-timer.c index 764e8b453ed4..10f4dbce9d1f 100644 --- a/drivers/clocksource/tegra-tsc-timer.c +++ b/drivers/clocksource/tegra-tsc-timer.c @@ -6,7 +6,7 @@ * Author: * Colin Cross <ccross@google.com> * - * Copyright (C) 2013 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2013-2014 NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -134,9 +134,9 @@ void __init tegra_cpu_timer_init(void) static void tegra_arch_timer_per_cpu_init(void) { -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) - return; -#else + if (!is_secure_mode()) + return; + if (arch_timer_initialized) { u32 tsc_ref_freq = tegra_clk_measure_input_freq(); @@ -151,7 +151,6 @@ static void tegra_arch_timer_per_cpu_init(void) NOTE: this is a write once (per CPU reset) register. */ __asm__("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (tsc_ref_freq)); } -#endif } static int arch_timer_cpu_notify(struct notifier_block *self, diff --git a/drivers/watchdog/tegra_wdt.c b/drivers/watchdog/tegra_wdt.c index 9cfe5a2780d4..91d25e3f2250 100644 --- a/drivers/watchdog/tegra_wdt.c +++ b/drivers/watchdog/tegra_wdt.c @@ -3,7 +3,7 @@ * * watchdog driver for NVIDIA tegra internal watchdog * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. * * based on drivers/watchdog/softdog.c and drivers/watchdog/omap_wdt.c * @@ -69,8 +69,7 @@ struct tegra_wdt { int tmrsrc; int timeout; int status; -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) struct resource *res_avp_src; void __iomem *wdt_avp_source; #endif @@ -155,11 +154,12 @@ struct tegra_wdt *tegra_wdt[MAX_NR_CPU_WDT]; static inline void tegra_wdt_ping(struct tegra_wdt *wdt) { writel(WDT_CMD_START_COUNTER, wdt->wdt_source + WDT_CMD); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - /* Comment out to test FIQ debugger */ - if (!watchdog_get_lockup_state()) - writel(WDT_CMD_START_COUNTER, wdt->wdt_avp_source + WDT_CMD); +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) + /* Comment out to test FIQ debugger */ + if (!watchdog_get_lockup_state()) + writel(WDT_CMD_START_COUNTER, wdt->wdt_avp_source + + WDT_CMD); #endif } @@ -204,13 +204,13 @@ static void tegra_wdt_enable(struct tegra_wdt *wdt) writel(val, wdt->wdt_source + WDT_CFG); writel(WDT_CMD_START_COUNTER, wdt->wdt_source + WDT_CMD); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - val = wdt->tmrsrc | (WDT_CFG_PERIOD << 1) | /*WDT_CFG_INT_EN |*/ - /*WDT_CFG_SYS_RST_EN |*/ WDT_CFG_PMC2CAR_RST_EN; - writel(val, wdt->wdt_avp_source + WDT_CFG); - writel(WDT_CMD_START_COUNTER, wdt->wdt_avp_source + WDT_CMD); - +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + val = wdt->tmrsrc | (WDT_CFG_PERIOD << 1) | /*WDT_CFG_INT_EN |*/ + /*WDT_CFG_SYS_RST_EN |*/ WDT_CFG_PMC2CAR_RST_EN; + writel(val, wdt->wdt_avp_source + WDT_CFG); + writel(WDT_CMD_START_COUNTER, wdt->wdt_avp_source + WDT_CMD); + } #endif } @@ -219,10 +219,11 @@ static void tegra_wdt_disable(struct tegra_wdt *wdt) writel(WDT_UNLOCK_PATTERN, wdt->wdt_source + WDT_UNLOCK); writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_source + WDT_CMD); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - writel(WDT_UNLOCK_PATTERN, wdt->wdt_avp_source + WDT_UNLOCK); - writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_avp_source + WDT_CMD); +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + writel(WDT_UNLOCK_PATTERN, wdt->wdt_avp_source + WDT_UNLOCK); + writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_avp_source + WDT_CMD); + } #endif writel(0, wdt->wdt_timer + TIMER_PTV); @@ -244,8 +245,7 @@ static irqreturn_t tegra_wdt_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) static irqreturn_t tegra_wdt_avp_interrupt(int irq, void *dev_id) { return IRQ_HANDLED; @@ -429,8 +429,7 @@ static const struct file_operations tegra_wdt_fops = { static int tegra_wdt_probe(struct platform_device *pdev) { struct resource *res_src, *res_wdt, *res_irq, *res_pmc; -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) struct resource *res_avp_src, *res_avp_irq; #endif struct resource *res_int_base = NULL; @@ -447,22 +446,31 @@ static int tegra_wdt_probe(struct platform_device *pdev) res_pmc = platform_get_resource(pdev, IORESOURCE_MEM, 2); res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - res_avp_src = platform_get_resource(pdev, IORESOURCE_MEM, 4); - res_avp_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + res_avp_src = platform_get_resource(pdev, IORESOURCE_MEM, 4); + res_avp_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + } #endif -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - if (!res_src || !res_wdt || !res_avp_src || (!pdev->id && !res_irq) || - !res_pmc) { +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + if (!res_src || !res_wdt || !res_avp_src || + (!pdev->id && !res_irq) || !res_pmc) { + dev_err(&pdev->dev, "incorrect resources\n"); + return -ENOENT; + } + } else if (!res_src || !res_wdt || (!pdev->id && !res_irq) + || !res_pmc) { + dev_err(&pdev->dev, "incorrect resources\n"); + return -ENOENT; + } #else if (!res_src || !res_wdt || (!pdev->id && !res_irq) || !res_pmc) { -#endif dev_err(&pdev->dev, "incorrect resources\n"); return -ENOENT; } +#endif #if !defined(CONFIG_ARCH_TEGRA_12x_SOC) || !defined(CONFIG_FIQ_DEBUGGER) #ifdef CONFIG_TEGRA_FIQ_DEBUGGER @@ -512,47 +520,67 @@ static int tegra_wdt_probe(struct platform_device *pdev) res_pmc = request_mem_region(res_pmc->start, resource_size(res_pmc), pdev->name); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - res_avp_src = request_mem_region(res_avp_src->start, +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) + res_avp_src = request_mem_region(res_avp_src->start, resource_size(res_avp_src), pdev->name); #endif -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - if (!res_src || !res_wdt || !res_avp_src || !res_pmc) { +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + if (!res_src || !res_wdt || !res_avp_src || !res_pmc) { + dev_err(&pdev->dev, "unable to request + memory resources\n"); + ret = -EBUSY; + goto fail; + } + } else if (!res_src || !res_wdt || !res_pmc) { + dev_err(&pdev->dev, "unable to request memory resources\n"); + ret = -EBUSY; + goto fail; + } + #else if (!res_src || !res_wdt || !res_pmc) { -#endif dev_err(&pdev->dev, "unable to request memory resources\n"); ret = -EBUSY; goto fail; } +#endif wdt->wdt_source = ioremap(res_src->start, resource_size(res_src)); wdt->wdt_timer = ioremap(res_wdt->start, resource_size(res_wdt)); wdt->pmc_base = ioremap(res_pmc->start, resource_size(res_pmc)); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - wdt->wdt_avp_source = ioremap(res_avp_src->start, +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) + wdt->wdt_avp_source = ioremap(res_avp_src->start, resource_size(res_avp_src)); #endif /* tmrsrc will be used to set WDT_CFG */ wdt->tmrsrc = (TMR_SRC_START + pdev->id) % 10; -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - if (!wdt->wdt_source || !wdt->wdt_timer || !wdt->wdt_avp_source || - !wdt->pmc_base) { +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + if (!wdt->wdt_source || !wdt->wdt_timer || + !wdt->wdt_avp_source || !wdt->pmc_base) { + dev_err(&pdev->dev, "unable to map registers\n"); + ret = -ENOMEM; + goto fail; + } + } else if (!wdt->wdt_source || !wdt->wdt_timer || !wdt->pmc_base) { + dev_err(&pdev->dev, "unable to map registers\n"); + ret = -ENOMEM; + goto fail; + } #else if (!wdt->wdt_source || !wdt->wdt_timer || !wdt->pmc_base) { -#endif dev_err(&pdev->dev, "unable to map registers\n"); ret = -ENOMEM; goto fail; } +#endif tegra_wdt_log_reset_reason(pdev, wdt); @@ -587,13 +615,16 @@ static int tegra_wdt_probe(struct platform_device *pdev) goto fail; } -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - ret = request_irq(res_avp_irq->start, tegra_wdt_avp_interrupt, +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + ret = request_irq(res_avp_irq->start, + tegra_wdt_avp_interrupt, IRQF_DISABLED, "avp_wdt", wdt); - if (ret) { - dev_err(&pdev->dev, "unable to configure WDT AVP IRQ\n"); - goto fail; + if (ret) { + dev_err(&pdev->dev, "unable to configure + WDT AVP IRQ\n"); + goto fail; + } } #endif @@ -602,9 +633,9 @@ static int tegra_wdt_probe(struct platform_device *pdev) wdt->res_src = res_src; -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - wdt->res_avp_src = res_avp_src; +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) + wdt->res_avp_src = res_avp_src; #endif wdt->res_wdt = res_wdt; wdt->res_int_base = res_int_base; @@ -638,12 +669,12 @@ static int tegra_wdt_probe(struct platform_device *pdev) val |= WDT_CFG_INT_EN; writel(val, wdt->wdt_source + WDT_CFG); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - val = readl(wdt->wdt_avp_source + WDT_CFG); - val |= WDT_CFG_INT_EN; - writel(val, wdt->wdt_avp_source + WDT_CFG); - +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + val = readl(wdt->wdt_avp_source + WDT_CFG); + val |= WDT_CFG_INT_EN; + writel(val, wdt->wdt_avp_source + WDT_CFG); + } #endif pr_info("WDT heartbeat enabled on probe\n"); } @@ -673,13 +704,14 @@ fail: if (res_pmc) release_mem_region(res_pmc->start, resource_size(res_pmc)); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - if (wdt->wdt_avp_source) - iounmap(wdt->wdt_avp_source); - if (res_avp_src) - release_mem_region(res_avp_src->start, +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + if (wdt->wdt_avp_source) + iounmap(wdt->wdt_avp_source); + if (res_avp_src) + release_mem_region(res_avp_src->start, resource_size(res_avp_src)); + } #endif kfree(wdt); return ret; @@ -697,9 +729,9 @@ static int tegra_wdt_remove(struct platform_device *pdev) free_irq(wdt->irq, wdt); iounmap(wdt->wdt_source); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - iounmap(wdt->wdt_avp_source); +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) + iounmap(wdt->wdt_avp_source); #endif iounmap(wdt->wdt_timer); if (wdt->int_base) @@ -708,9 +740,9 @@ static int tegra_wdt_remove(struct platform_device *pdev) iounmap(wdt->pmc_base); release_mem_region(wdt->res_src->start, resource_size(wdt->res_src)); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - release_mem_region(wdt->res_avp_src->start, +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) + release_mem_region(wdt->res_avp_src->start, resource_size(wdt->res_avp_src)); #endif release_mem_region(wdt->res_wdt->start, resource_size(wdt->res_wdt)); @@ -749,11 +781,12 @@ static int tegra_wdt_resume(struct platform_device *pdev) val |= WDT_CFG_INT_EN; writel(val, wdt->wdt_source + WDT_CFG); -#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL) && \ - defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) - val = readl(wdt->wdt_avp_source + WDT_CFG); - val |= WDT_CFG_INT_EN; - writel(val, wdt->wdt_avp_source + WDT_CFG); +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_FIQ_DEBUGGER) + if (!is_secure_mode()) { + val = readl(wdt->wdt_avp_source + WDT_CFG); + val |= WDT_CFG_INT_EN; + writel(val, wdt->wdt_avp_source + WDT_CFG); + } #endif pr_info("WDT heartbeat enabled on probe\n"); } diff --git a/include/linux/tegra-soc.h b/include/linux/tegra-soc.h index 7d3b69af1ffb..b72794cf39c6 100644 --- a/include/linux/tegra-soc.h +++ b/include/linux/tegra-soc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -57,6 +57,7 @@ unsigned int tegra_get_minor_rev(void); int tegra_get_lane_owner_info(void); int tegra_split_mem_active(void); +int is_secure_mode(void); #ifdef CONFIG_TEGRA_PRE_SILICON_SUPPORT void tegra_get_netlist_revision(u32 *netlist, u32* patchid); diff --git a/security/tf_driver/Kconfig b/security/tf_driver/Kconfig index e212e53913eb..49b34b37bb4f 100644 --- a/security/tf_driver/Kconfig +++ b/security/tf_driver/Kconfig @@ -2,7 +2,6 @@ config TRUSTED_FOUNDATIONS bool "Enable TF Driver" default n select CRYPTO_SHA1 - select TEGRA_USE_SECURE_KERNEL help This option adds kernel support for communication with the Trusted Foundations. Default options is n diff --git a/security/tlk_driver/Kconfig b/security/tlk_driver/Kconfig index 5199be43dd20..b87d6d820a57 100644 --- a/security/tlk_driver/Kconfig +++ b/security/tlk_driver/Kconfig @@ -1,6 +1,5 @@ config TRUSTED_LITTLE_KERNEL bool "Enable Open Trusted Execution driver" - select TEGRA_USE_SECURE_KERNEL help This option adds kernel support for communication with the Trusted LK secure OS monitor/runtime support. |