asoc: tegra: spdif: update registers

Update registers to meet t12x spdif controller specs

Bug 1448381

Change-Id: I67f9f1e7fe2a50028214a784d0aedabf3e3691d1
Signed-off-by: Andy Park <andyp@nvidia.com>
Signed-off-by: Arun Kannan <akannan@nvidia.com>
Reviewed-on: http://git-master/r/385845
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
GVS: Gerrit_Virtual_Submit

2 files changed, 60 insertions, 40 deletions

diff --git a/sound/soc/tegra/tegra30_spdif.c b/sound/soc/tegra/tegra30_spdif.c
index c5355f90e0bc..0b54da7ba825 100644
--- a/sound/soc/tegra/tegra30_spdif.c
+++ b/sound/soc/tegra/tegra30_spdif.c
@@ -5,7 +5,7 @@
  *
  * Based on code copyright/by:
  *
- * Copyright (c) 2009-2013 NVIDIA Corporation.  All Rights Reserved.
+ * Copyright (c) 2009-2014 NVIDIA Corporation.  All Rights Reserved.
  * Scott Peterson <speterson@nvidia.com>
  *
  * Copyright (C) 2010 Google, Inc.
@@ -37,7 +37,6 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/clk/tegra.h>
-#include <mach/hdmi-audio.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/pcm_params.h>
@@ -218,7 +217,6 @@ static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
 	spdif->reg_ctrl &= ~TEGRA30_SPDIF_CTRL_BIT_MODE_MASK;
 	switch (params_format(params)) {
 	case SNDRV_PCM_FORMAT_S16_LE:
-		spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_PACK_ENABLE;
 		spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT;
 		break;
 	default:
@@ -288,21 +286,6 @@ static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
 		return ret;
 	}
 
-	tegra30_spdif_enable_clocks(spdif);
-
-	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_A,
-						spdif->reg_ch_sta_a);
-	tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_B,
-						spdif->reg_ch_sta_b);
-
-	tegra30_spdif_disable_clocks(spdif);
-
-	ret = tegra_hdmi_setup_audio_freq_source(srate, SPDIF);
-	if (ret) {
-		dev_err(dev, "Can't set HDMI audio freq source: %d\n", ret);
-		return ret;
-	}
-
 	return 0;
 }
 
diff --git a/sound/soc/tegra/tegra30_spdif.h b/sound/soc/tegra/tegra30_spdif.h
index c4763c31b257..eab350242634 100644
--- a/sound/soc/tegra/tegra30_spdif.h
+++ b/sound/soc/tegra/tegra30_spdif.h
@@ -2,11 +2,10 @@
  * tegra30_spdif.h - Definitions for Tegra30 SPDIF driver
  *
  * Author: Sumit Bhattacharya <sumitb@nvidia.com>
- * Copyright (C) 2011 - NVIDIA, Inc.
  *
  * Based on code copyright/by:
  *
- * Copyright (c) 2009-2011, NVIDIA Corporation.
+ * Copyright (c) 2009-2014 NVIDIA Corporation.  All Rights Reserved.
  * Scott Peterson <speterson@nvidia.com>
  *
  * Copyright (C) 2010 Google, Inc.
@@ -214,9 +213,40 @@
 #define TEGRA30_SPDIF_CIF_CH7				6
 #define TEGRA30_SPDIF_CIF_CH8				7
 
+#ifdef CONFIG_ARCH_TEGRA_12x_SOC
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT	20
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT	20
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT	20
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT	20
+#define TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN		0xf
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_CTRL_FIFO_TH_MASK_LEN		0x3f
+
+#else
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT	24
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT	24
+#define TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN		0x7
+
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT	28
+#define TEGRA30_SPDIF_CIF_CTRL_FIFO_TH_MASK_LEN		0x7
+
+#endif
+
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT	16
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH2		\
@@ -235,9 +265,9 @@
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXD_CTRL_CLIENT_CH_SHIFT)
 
 
-#define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT	24
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH2		\
@@ -255,8 +285,9 @@
 #define TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH8		\
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXD_CTRL_AUDIO_CH_SHIFT)
 
-#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT	28
-#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_MASK		(0x7 << TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_MASK			\
+		(TEGRA30_SPDIF_CIF_CTRL_FIFO_TH_MASK_LEN <<	\
+		TEGRA30_SPDIF_CIF_TXD_CTRL_FIFO_TH_SHIFT)
 
 /* Fields in TEGRA30_TEGRA30_SPDIF_CIF_RXD_CTRL */
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_MONO_CONV_COPY	(1<<0)
@@ -332,7 +363,8 @@
 
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT 16
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH2		\
@@ -351,9 +383,9 @@
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXD_CTRL_CLIENT_CH_SHIFT)
 
 
-#define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT	24
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH2		\
@@ -371,8 +403,9 @@
 #define TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CH8		\
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXD_CTRL_AUDIO_CHANNELS_SHIFT)
 
-#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT	28
-#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_MASK		(0x7  << TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_MASK			\
+		(TEGRA30_SPDIF_CIF_CTRL_FIFO_TH_MASK_LEN <<	\
+		TEGRA30_SPDIF_CIF_RXD_CTRL_FIFO_TH_SHIFT)
 
 /* Fields in TEGRA30_TEGRA30_SPDIF_CIF_TXU_CTRL */
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_MONO_CONV_COPY	(1<<0)
@@ -451,7 +484,8 @@
 
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT 16
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH2		\
@@ -470,9 +504,9 @@
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXU_CTRL_CLIENT_CH_SHIFT)
 
 
-#define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT	24
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH2		\
@@ -490,8 +524,9 @@
 #define TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH8		\
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_TXU_CTRL_AUDIO_CH_SHIFT)
 
-#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT	28
-#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_MASK		(0x7 << TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT)
+#define TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_MASK			\
+		(TEGRA30_SPDIF_CIF_CTRL_FIFO_TH_MASK_LEN <<	\
+		TEGRA30_SPDIF_CIF_TXU_CTRL_FIFO_TH_SHIFT)
 
 /* Fields in TEGRA30_TEGRA30_SPDIF_CIF_RXU_CTRL */
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_MONO_CONV_COPY	(1<<0)
@@ -570,7 +605,8 @@
 
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT 16
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH2		\
@@ -589,9 +625,9 @@
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXU_CTRL_CLIENT_CH_SHIFT)
 
 
-#define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT	24
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_MASK	\
-		(0x7                   << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
+		(TEGRA30_SPDIF_CIF_CTRL_CH_MASK_LEN <<	\
+		 TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH1		\
 		(TEGRA30_SPDIF_CIF_CH1 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH2		\
@@ -609,8 +645,9 @@
 #define TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH8		\
 		(TEGRA30_SPDIF_CIF_CH8 << TEGRA30_SPDIF_CIF_RXU_CTRL_AUDIO_CH_SHIFT)
 
-#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT	28
-#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_MASK		(0x7 << TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT)
+#define TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_MASK			\
+		(TEGRA30_SPDIF_CIF_CTRL_FIFO_TH_MASK_LEN <<	\
+		TEGRA30_SPDIF_CIF_RXU_CTRL_FIFO_TH_SHIFT)
 
 /* Fields in TEGRA30_SPDIF_CH_STA_RX_A */
 /* Fields in TEGRA30_SPDIF_CH_STA_RX_B */