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| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2014-05-23 13:41:55 -0700 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-05-29 01:49:38 -0700 |
| commit | 392b7dbbf3d76f2db05eea05bcf8e1bd9610220b (patch) | |
| tree | ca573e644bdc0c6d4f66334bb214dbef00926c56 /fs | |
| parent | 8dc7d4e81471a8bdaa5f51225bf45812f7641185 (diff) | |
arm: tegra: soctherm: refactor throt level & vect.
CPU HW throttling configuration is done in two stages. First stage in
soctherm register space has a vector and the second stage in CCROC
register space has the depths for each of these vectors. Although
there are only 3 vectors, no-vector is also a valid configuration.
Changed code to allow for NONE vector and use that for OC5. Also
modified debug show command to display throttle depth and vector
information as per new format.
Bug 200006274
Change-Id: Ie56a99a4eeff44c033ed69beadbee1987a86c903
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/414262
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com>
Diffstat (limited to 'fs')
0 files changed, 0 insertions, 0 deletions