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authorLaxman Dewangan <ldewangan@nvidia.com>2010-07-11 15:16:58 +0530
committerGary King <gking@nvidia.com>2010-07-13 12:36:08 -0700
commit93513be66fbc0770f849d0a6996692d50a923525 (patch)
tree7847060a26711df5e4e6edc69e7233e246ccbb1f /drivers
parent32efa0b83a91b12a0df1b37550a9d154b9c907ce (diff)
[arm/tegra] serial: Removing tx fifo empty wait after each tx.
When dma is used to transmit the data through uart, there is a wait to become the tx fifo empty after each tx dma complete. This wait is not required after each dma transfer complete because the next dma/pio based transfer can start even if tx fifo is not empty. Th uart controller only req dma when there is space in tx fifo. The correct state will be returned from the function of tx_empty based on tx state and fifo status. Change-Id: I3eb34e26d68b8a3d214759c23b89ef6585881729 Reviewed-on: http://git-master.nvidia.com/r/3782 Reviewed-by: Anantha Idapalapati <aidapalapati@nvidia.com> Tested-by: Anantha Idapalapati <aidapalapati@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'drivers')
-rwxr-xr-xdrivers/serial/tegra_hsuart.c19
1 files changed, 6 insertions, 13 deletions
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c
index fc4dd8c7d791..5db6096da828 100755
--- a/drivers/serial/tegra_hsuart.c
+++ b/drivers/serial/tegra_hsuart.c
@@ -426,20 +426,9 @@ static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
struct circ_buf *xmit = &t->uport.state->xmit;
int count = req->bytes_transferred;
unsigned long flags;
- int timeout = 20;
dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count);
- while ((uart_readb(t, UART_LSR) & TX_EMPTY_STATUS) != TX_EMPTY_STATUS) {
- timeout--;
- if (timeout == 0) {
- dev_err(t->uport.dev,
- "timed out waiting for TX FIFO to empty\n");
- return;
- }
- msleep(1);
- }
-
spin_lock_irqsave(&t->uport.lock, flags);
xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
t->tx_in_progress = 0;
@@ -895,13 +884,17 @@ static unsigned int tegra_tx_empty(struct uart_port *u)
struct tegra_uart_port *t;
unsigned int ret = 0;
unsigned long flags;
+ unsigned char lsr;
t = container_of(u, struct tegra_uart_port, uport);
dev_vdbg(u->dev, "+tegra_tx_empty\n");
spin_lock_irqsave(&u->lock, flags);
- if (!t->tx_in_progress)
- ret = TIOCSER_TEMT;
+ if (!t->tx_in_progress) {
+ lsr = uart_readb(t, UART_LSR);
+ if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
+ ret = TIOCSER_TEMT;
+ }
spin_unlock_irqrestore(&u->lock, flags);
dev_vdbg(u->dev, "-tegra_tx_empty\n");