diff options
author | BH Hsieh <bhsieh@nvidia.com> | 2014-04-14 15:25:34 +0800 |
---|---|---|
committer | Riham Haidar <rhaidar@nvidia.com> | 2014-06-09 20:58:13 -0700 |
commit | 082b973c819a6e28c1e5cdb8fb94a1ae53f4613e (patch) | |
tree | 47508d9ab8c878c073db482617be5254de1a08a6 /drivers/usb | |
parent | 72a7785e69c7be2797709810976b0103a652749d (diff) |
usb: phy: tegra: HSIC: Clear PD_TX during resume
During HSIC resume the PD_TX circuit is to be turned on before
clearing MASTER_ENABLE of PMC.
Bug 1496758
Change-Id: I1127dfc0fc0e3b8dfb63bafa2291483186e06093
Signed-off-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-on: http://git-master/r/395683
(cherry picked from commit I1127dfc0fc0e3b8dfb63bafa2291483186e06093)
Reviewed-on: http://git-master/r/420336
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Martin Chi <mchi@nvidia.com>
Tested-by: Martin Chi <mchi@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r-- | drivers/usb/phy/tegra11x_usb_phy.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/drivers/usb/phy/tegra11x_usb_phy.c b/drivers/usb/phy/tegra11x_usb_phy.c index 3361e27151af..71758e2fb5c8 100644 --- a/drivers/usb/phy/tegra11x_usb_phy.c +++ b/drivers/usb/phy/tegra11x_usb_phy.c @@ -2109,6 +2109,13 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) phy->ctrlr_suspended = false; } + val = tegra_usb_pmc_reg_read(PMC_UHSIC_SLEEP_CFG(phy->inst)); + if (val & UHSIC_MASTER_ENABLE(phy->inst)) { + val = readl(base + UHSIC_PADS_CFG1); + val &= ~(UHSIC_PD_TX); + writel(val, base + UHSIC_PADS_CFG1); + } + pmc->pmc_ops->disable_pmc_bus_ctrl(pmc, 1); phy->pmc_remote_wakeup = false; @@ -2327,9 +2334,12 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + USB_SUSP_CTRL); udelay(1); - val = readl(base + UHSIC_PADS_CFG1); - val &= ~(UHSIC_PD_TX); - writel(val, base + UHSIC_PADS_CFG1); + val = tegra_usb_pmc_reg_read(PMC_UHSIC_SLEEP_CFG(phy->inst)); + if (!(val & UHSIC_MASTER_ENABLE(phy->inst))) { + val = readl(base + UHSIC_PADS_CFG1); + val &= ~(UHSIC_PD_TX); + writel(val, base + UHSIC_PADS_CFG1); + } /* HSIC pad tracking circuit power down sequence */ val = readl(base + UHSIC_PADS_CFG1); |