diff options
| author | joyw <joyw@nvidia.com> | 2013-09-12 14:47:54 +0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-27 12:54:02 -0700 |
| commit | e6352c9818d99af96158059e8ffe87baa2e612fe (patch) | |
| tree | 5fe8cce4582c6539a5edd39e81e16173a05121d0 /drivers/usb/host/xhci-tegra.c | |
| parent | 41a752465c4dc5ee5b0efc29defeb2d9415f434a (diff) | |
xhci: tegra: Add support for xusb use sata lane
For some boards, Laguna, use sata lane for SS port 1. Add
support to set relevant register,XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL_*_0,
in pad ctontrol.
Bug 1366525
Change-Id: I409843c9a8d67ab5438357d550f7ddda0fda4495
Signed-off-by: joyw <joyw@nvidia.com>
Reviewed-on: http://git-master/r/273556
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/usb/host/xhci-tegra.c')
| -rw-r--r-- | drivers/usb/host/xhci-tegra.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index d9a4f093d3c9..c0a2ace5644a 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -2116,6 +2116,13 @@ static void tegra_xhci_program_utmip_pad(struct tegra_xhci_hcd *tegra, tegra_xhci_release_otg_port(true); } +static inline bool xusb_use_sata_lane(struct tegra_xhci_hcd *tegra) +{ + return ((XUSB_DEVICE_ID_T114 == tegra->device_id) ? false + : ((tegra->bdata->portmap & TEGRA_XUSB_SS_P1) + && (tegra->bdata->lane_owner & BIT(0)))); +} + static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra, u8 port) { @@ -2150,6 +2157,17 @@ static void tegra_xhci_program_ss_pad(struct tegra_xhci_hcd *tegra, reg |= SPARE_IN(tegra->pdata->spare_in); writel(reg, tegra->padctl_base + MISC_PAD_CTL_2_0(port)); + if (xusb_use_sata_lane(tegra)) { + reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_5_0); + reg |= RX_QEYE_EN; + writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_5_0); + + reg = readl(tegra->padctl_base + MISC_PAD_S0_CTL_2_0); + reg &= ~SPARE_IN(~0); + reg |= SPARE_IN(tegra->pdata->spare_in); + writel(reg, tegra->padctl_base + MISC_PAD_S0_CTL_2_0); + } + reg = readl(tegra->padctl_base + padregs->ss_port_map_0); reg &= ~(port ? SS_PORT_MAP_P1 : SS_PORT_MAP_P0); reg |= (tegra->bdata->ss_portmap & |