diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2012-10-01 17:03:22 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:13:06 -0700 |
| commit | 9d9ad24a990b5d50a81e297a05f9a3740049a340 (patch) | |
| tree | b502edddd12b4247c1db8a47e3cce7582b906056 /drivers/spi | |
| parent | 81b47eb8690c8ac42cf1acbf66d13462e3ecd519 (diff) | |
spi: tegra11: support for rx/tx clock tap delay
The spi tegra11 have the configuration for rx and tx
clock tap delay which need to be configure based on
the spi interface speed. It also depends on the platform
on which it is running.
Addign support for configuring this parameter through
platform file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/140615
(cherry picked from commit b7742640eb264677a47f9944b7711ddbf07bd723)
Change-Id: I4caa2a8405d56f9d85622f540fe6b36e49c2bf39
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/143269
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R26ddc25bd03148f6d366f1e2e336eb91f40d619f
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-tegra11.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/drivers/spi/spi-tegra11.c b/drivers/spi/spi-tegra11.c index 8c86c6249253..761f793266c0 100644 --- a/drivers/spi/spi-tegra11.c +++ b/drivers/spi/spi-tegra11.c @@ -79,8 +79,8 @@ #define SPI_PIO (1 << 31) #define SPI_COMMAND2 0x004 -#define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 0) -#define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 6) +#define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6) +#define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0) #define SPI_CS_TIM1 0x008 #define SPI_CS_HOLD_TIME_0(x) (((x) & 0xF) << 0) @@ -244,7 +244,6 @@ struct spi_tegra_data { bool is_packed; u32 command1_reg; - u32 command2_reg; u32 dma_control_reg; u32 def_command1_reg; u32 def_command2_reg; @@ -713,6 +712,7 @@ static void spi_tegra_start_transfer(struct spi_device *spi, int ret; unsigned long command1; int req_mode; + struct tegra_spi_device_controller_data *cdata = spi->controller_data; bits_per_word = t->bits_per_word ? t->bits_per_word : spi->bits_per_word; @@ -759,6 +759,20 @@ static void spi_tegra_start_transfer(struct spi_device *spi, command1 &= ~SPI_CS_SS_VAL; } + if (cdata) { + u32 command2_reg; + u32 rx_tap_delay; + u32 tx_tap_delay; + + rx_tap_delay = min(cdata->rx_clk_tap_delay, 63); + tx_tap_delay = min(cdata->tx_clk_tap_delay, 63); + command2_reg = SPI_TX_TAP_DELAY(tx_tap_delay) | + SPI_RX_TAP_DELAY(tx_tap_delay); + spi_tegra_writel(tspi, command2_reg, SPI_COMMAND2); + } else { + spi_tegra_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); + } + command1 &= ~SPI_CONTROL_MODE_MASK; req_mode = spi->mode & 0x3; if (req_mode == SPI_MODE_0) @@ -1402,6 +1416,7 @@ skip_dma_alloc: SPI_CS_POL_INACTIVE_3 | SPI_CS_SS_VAL | SPI_LSBYTE_FE; tegra_spi_clk_enable(tspi); spi_tegra_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); + tspi->def_command2_reg = spi_tegra_readl(tspi, SPI_COMMAND2); tegra_spi_clk_disable(tspi); pm_runtime_enable(&pdev->dev); @@ -1546,6 +1561,7 @@ static int spi_tegra_resume(struct device *dev) pm_runtime_get_sync(dev); tegra_spi_clk_enable(tspi); spi_tegra_writel(tspi, tspi->command1_reg, SPI_COMMAND1); + spi_tegra_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); tegra_spi_clk_disable(tspi); pm_runtime_put_sync(dev); |