summaryrefslogtreecommitdiff
path: root/drivers/spi
diff options
context:
space:
mode:
authorKunal Agrawal <kunala@nvidia.com>2012-09-25 20:52:49 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 01:13:04 -0700
commit48b9defd6567638e323451389cbc915b8cba036e (patch)
treec89864e9603f0894e171f39db7839cb5a81e2396 /drivers/spi
parentacfc0ff251f7a02ac8883b177929f356eb7785e3 (diff)
spi: tegra: fix dma based transfer issue
Tegra11 spi controller not require the Tx fifo to be fill before enabling dma. Removing this checks. Signed-off-by: Kunal Agrawal <kunala@nvidia.com> Reviewed-on: http://git-master/r/135160 (cherry picked from commit c9f0787bd10a9dc17eeb6587a67493e0d042160a) Change-Id: I366c191b9db6d713389307a1bc9904b2d8b0b064 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/143266 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Re0d82749b714584d6ee14c567d37d91379dd133b
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-tegra11.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/spi/spi-tegra11.c b/drivers/spi/spi-tegra11.c
index de595e065a46..976b6585d16d 100644
--- a/drivers/spi/spi-tegra11.c
+++ b/drivers/spi/spi-tegra11.c
@@ -545,7 +545,7 @@ static int spi_tegra_start_dma_based_transfer(
/* Make sure that Rx and Tx fifo are empty */
test_val = spi_tegra_readl(tspi, SPI_FIFO_STATUS);
- if (((test_val >> 16) & 0x3FFF) != 0x7F)
+ if (((test_val >> 16) & 0x3FFF) != 0x40)
dev_err(&tspi->pdev->dev,
"The Rx and Tx fifo are not empty status 0x%08lx\n",
test_val);
@@ -586,11 +586,6 @@ static int spi_tegra_start_dma_based_transfer(
"Error in starting tx dma error = %d\n", ret);
return ret;
}
-
- /* Wait for tx fifo to be fill before starting SPI */
- test_val = spi_tegra_readl(tspi, SPI_FIFO_STATUS);
- while (!(test_val & SPI_TX_FIFO_FULL))
- test_val = spi_tegra_readl(tspi, SPI_FIFO_STATUS);
}
if (tspi->cur_direction & DATA_DIR_RX) {
@@ -639,6 +634,7 @@ static int spi_tegra_start_cpu_based_transfer(
spi_tegra_writel(tspi, val, SPI_DMA_CTL);
tspi->dma_control_reg = val;
+ tspi->is_curr_dma_xfer = false;
val = tspi->command1_reg;
val |= SPI_PIO;
spi_tegra_writel(tspi, val, SPI_COMMAND1);