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authorMallikarjun Kasoju <mkasoju@nvidia.com>2013-12-26 23:25:51 +0530
committerLaxman Dewangan <ldewangan@nvidia.com>2014-01-09 01:21:18 -0800
commit1ac2ba8841d53c5e4914e2a515c6e005ee4003f5 (patch)
treee35d0eb7d0e674f370c2c8146bf4afb3acd2fdb1 /drivers/pinctrl
parent41f0aeb44644e331dc0414c564b9cbc739afece4 (diff)
pinctrl: as3722: set pin mode to output
If pins are used for function output like pwm, clk32k, power good etc then set it as output mode by default. Change-Id: I3ec3066f34c8a360f55bf6187f177509f79c6c06 Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com> Reviewed-on: http://git-master/r/349796 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/352238 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c24
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index 483a4c8f444a..c09c6b529719 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -1,7 +1,7 @@
/*
* ams AS3722 pin control and GPIO driver.
*
- * Copyright (c) 2013, NVIDIA Corporation.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* Author: Laxman Dewangan <ldewangan@nvidia.com>
*
@@ -250,6 +250,28 @@ static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
return ret;
}
as_pci->gpio_control[group].io_function = function;
+ val = val & AS3722_GPIO_IOSF_MASK;
+
+ switch (val) {
+ case AS3722_GPIO_IOSF_SD0_OUT:
+ case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
+ case AS3722_GPIO_IOSF_Q32K_OUT:
+ case AS3722_GPIO_IOSF_PWM_OUT:
+ case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
+ ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
+ AS3722_GPIO_MODE_MASK,
+ AS3722_GPIO_MODE_OUTPUT_VDDH);
+ if (ret < 0) {
+ dev_err(as_pci->dev,
+ "GPIO%d_CTRL_REG update failed %d\n",
+ group, ret);
+
+ return ret;
+ }
+ as_pci->gpio_control[group].mode_prop =
+ AS3722_GPIO_MODE_OUTPUT_VDDH;
+ }
+
return ret;
}