diff options
| author | Wojciech Bieganski <wbieganski@antmicro.com> | 2017-02-08 12:15:48 +0100 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-04-04 13:45:40 +0200 |
| commit | a91a076d29abed946577f1c002a5f62fce1ef9e7 (patch) | |
| tree | 6efe93d0c63b904d48f1a800a06939de80baf225 /drivers/media/platform/soc_camera/tegra_camera/vi2.c | |
| parent | eb6ceee5ed319d72bb98cdc4cda4685199e30d9a (diff) | |
media: tegra_camera: add continuous clk support
Signed-off-by: Wojciech Bieganski <wbieganski@antmicro.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'drivers/media/platform/soc_camera/tegra_camera/vi2.c')
| -rw-r--r-- | drivers/media/platform/soc_camera/tegra_camera/vi2.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/media/platform/soc_camera/tegra_camera/vi2.c b/drivers/media/platform/soc_camera/tegra_camera/vi2.c index a027c1c95f03..fb03bb7854b1 100644 --- a/drivers/media/platform/soc_camera/tegra_camera/vi2.c +++ b/drivers/media/platform/soc_camera/tegra_camera/vi2.c @@ -637,8 +637,10 @@ static int vi2_capture_setup_csi_0(struct tegra_camera_dev *cam, 0x3 | (0x1 << 5) | (0x40 << 8)); #endif - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILA_CONTROL0, 0x45); - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILB_CONTROL0, 0x45); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILA_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILB_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPA_COMMAND, 0xf007); TC_VI_REG_WT(cam, TEGRA_CSI_CSI_PIXEL_PARSER_A_INTERRUPT_MASK, 0x0); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_A_CONTROL0, 0x280301f0); @@ -742,10 +744,13 @@ static int vi2_capture_setup_csi_1(struct tegra_camera_dev *cam, #endif if (pdata->port == TEGRA_CAMERA_PORT_CSI_B) { - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILC_CONTROL0, 0x45); - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILD_CONTROL0, 0x45); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILC_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILD_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); } else if (pdata->port == TEGRA_CAMERA_PORT_CSI_C) - TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILE_CONTROL0, 0x45); + TC_VI_REG_WT(cam, TEGRA_CSI_PHY_CILE_CONTROL0, + ((pdata->continuous_clk << 6) | 0x05)); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, 0xf007); TC_VI_REG_WT(cam, TEGRA_CSI_CSI_PIXEL_PARSER_B_INTERRUPT_MASK, 0x0); |