diff options
| author | Bryan Wu <pengw@nvidia.com> | 2014-11-17 11:39:35 -0800 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2014-11-20 11:20:17 -0800 |
| commit | 8d56fa4d6f219fabcd271123265ccb78fbb723d3 (patch) | |
| tree | 2eb59ac30aec5ce45f8345e3900c147bd7a0921a /drivers/media/platform/soc_camera/tegra_camera/vi2.c | |
| parent | ef19d27ca4d97fe8b4f81dc994e3e4d633b13d0c (diff) | |
media: tegra_camera: bypass pixel transform
Disable pixel transform for our L4T/V42L use case.
This patch also add some missing settings for CSI-B.
Bug 1579773
Change-Id: I0f7d81799e5edcae80329d9bdf3d5c56fa9c295d
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/604312
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Diffstat (limited to 'drivers/media/platform/soc_camera/tegra_camera/vi2.c')
| -rw-r--r-- | drivers/media/platform/soc_camera/tegra_camera/vi2.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/drivers/media/platform/soc_camera/tegra_camera/vi2.c b/drivers/media/platform/soc_camera/tegra_camera/vi2.c index 0edaac05ccdf..c040cfae2a23 100644 --- a/drivers/media/platform/soc_camera/tegra_camera/vi2.c +++ b/drivers/media/platform/soc_camera/tegra_camera/vi2.c @@ -517,7 +517,8 @@ static int vi2_capture_setup_csi_0(struct tegra_camera_dev *cam, icd->user_width * 3); } else { /* output format RAW10 T_R16_I, only support direct to mem */ - TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_IMAGE_DEF, (32 << 16) | 0x1); + TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_IMAGE_DEF, + (1 << 24) | (32 << 16) | 0x1); /* input format is RAW10 */ TC_VI_REG_WT(cam, TEGRA_VI_CSI_0_CSI_IMAGE_DT, 43); @@ -539,7 +540,7 @@ static int vi2_capture_setup_csi_1(struct tegra_camera_dev *cam, TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, 0xf007); TC_VI_REG_WT(cam, TEGRA_CSI_CSI_PIXEL_PARSER_B_INTERRUPT_MASK, 0x0); - TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_B_CONTROL0, 0x280301f0); + TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_B_CONTROL0, 0x280301f1); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_PPB_COMMAND, 0xf007); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_B_CONTROL1, 0x11); TC_VI_REG_WT(cam, TEGRA_CSI_PIXEL_STREAM_B_GAP, 0x140000); @@ -569,14 +570,23 @@ static int vi2_capture_setup_csi_1(struct tegra_camera_dev *cam, TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_IMAGE_DEF, (64 << 16) | 0x1); /* input format is RGB888 */ TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_CSI_IMAGE_DT, 36); + + TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_CSI_IMAGE_SIZE_WC, + icd->user_width * 3); + } else { + /* output format RAW10 T_R16_I, only support direct to mem */ + TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_IMAGE_DEF, + (1 << 24) | (32 << 16) | 0x1); + /* input format is RAW10 */ + TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_CSI_IMAGE_DT, 43); + + TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_CSI_IMAGE_SIZE_WC, + icd->user_width * 10 / 8); } TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_CSI_IMAGE_SIZE, (icd->user_height << 16) | icd->user_width); - TC_VI_REG_WT(cam, TEGRA_VI_CSI_1_CSI_IMAGE_SIZE_WC, - icd->user_width * 3); - return 0; } |